System Level Performance Estimation Using Calibrated Weight Table Approach

Presenter: Smit Patel

Research Category: Engineering and Technology
Student Type: Graduate
PI: Gunar Schirner

In Electronic System Level Design it is essential to gauge the design decision at each level of abstraction while synthesizing from system level to the implementation. With an exploding Design Space, performance estimation at the highest abstraction level (Source-Level) is a critical step in embedded system design. The high level estimation must be capable of evaluating large number of design alternatives rapidly without compromising fidelity.

The proposed approach is based on populating the weight table of each Processing Element (PE) in the Design Space with automatic calibration and Linear Programming Formulation (LPF). Weight table captures performance cost of each processing operation determined by LPF. Automatic calibration uses dynamic profiling to extract maximum target characteristics, reflected at Source-Level. Another key feature of the proposed methodology is the ability to distinguish various software and hardware configurations which are not directly reflected at Source-Level. Once the weight tables of each PE in the Design Space are calculated, their performance towards an application can be speculated by profiling the application once and statically estimating the performance using the weight tables and application profile data.

The proposed approach is implemented on two different PEs, four different software configurations and two hardware configurations. This technique estimates with 24% average error, 90% fidelity and takes less than a second to complete. The absolute error is high compared to Binary-Level estimation techniques due to the fact that this estimation is at Source-Level, retargetable and extremely fast to evaluate the large Design Space with an acceptable fidelity rate.