Reducing Area Overhead of Phase Interpolator By Using Proposed Phase Error Monitor in Clock and Data Recovery

Presenter: Gyunam Jeon

Research Category: Engineering and Technology
PI: Gyunam Jeon

The poster presents low power 4Gbps clock and data recovery (CDR) by using improved phase interpolator (PI) with error monitor. The conventional CDR has eight sets of phase interpolators, but the proposed CDR architecture has only two sets of phase interpolator. Each set of the PI is comprised of eight inverters to get 11.25° phase interpolation from 0° to 348.75° by using the proposed phase error monitor. The outputs of phase error monitor are composed of 9 bits which are sampled from early pulse. The monitor chooses four clock phases among 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315° from an analog voltage controlled oscillator (VCO) by sending 3 bits to the mutiplexer. Then, the other 6 bits determine the interpolation phase of each block by using the inverter switches. For fast locking time, pre-charge to 350mV at the node of the Vcont (control voltage in VCO) is used. The time for frequency locking and phase selection are 23.35ns with pre-charge time (1.1ns). The design is simulated by a 180nm CMOS technology node with 1.8V power supply. The total power consumption is 4.35mW of the proposed CDR.