A Built-In Calibration System with A Reduced FFT Engine for Linearity Optimization of Low Power LNA

Research Category: Engineering and Technology
Presenter: Yongsuk Choi
PI: Yong-Bin Kim

A digital built-in calibration (BIC) system with a power and area optimized on-chip fast Fourier transform (FFT) engine is presented to automatically adjust the linearity of a tunable RF low-noise amplifier (LNA) operating at 2.4GHz. An envelope detection circuit is used to extract the linearity characteristics at low frequencies, enabling the sampling and digital signal processing at low rates. The output of the envelope detector is digitized before the spectrum calculation with the integrated FFT for estimation of the third-order intermodulation (IM3) distortion specification of the LNA. The digitally-assisted closed-loop calibration scheme is demonstrated with simulations using a two-tone test with 1MHz tone spacing, a 512-point FFT engine, a 10-bit analog-to-digital converter (ADC) model, and digital blocks operating with a 51.2MHz clock frequency. In order to validate the proposed BIC technique with device mismatch effects, Monte Carlo simulations are performed at transient simulations. The RF/analog and digital blocks were implemented using a standard 0.13μm CMOS technology.