A 10-Gb/s Serial-Link Receiver Design for USB 3.1 with a Continuous-Time Linear Equalizer and 1-Tap DFE

2016
Research Category: Engineering and Technology
Presenter: Yongsuk Choi
PI: Yong-Bin Kim

This paper presents a wire-line receiver design of CMOS I/O at 10-Gb/s data rate for USB 3.1 standard. A power efficient continuous time linear equalizer (CTLE) and 1-tap look-ahead decision feedback equalizer (DFE) are designed and implemented in a 45nm CMOS technology. The DFE employs a sampler including a current injection section that makes no use of summer as a separated block. In addition, cascode structure increases kick-back noise immunity and reduces power consumption by 11%. The PLL used in the proposed receiver drives 5 GHz clock frequency with 12.62 ps of peak-to-peak jitter. The core receiver circuit consumes 14.3 mW at a 1.1 V supply voltage when processing 10 Gb/s data rate with 15 dB of channel loss at Nyquist frequency.

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