Integration of RTOS into Electronic System Level Design
Lead Presenter: Rohan Kangralkar
Faculty Advisor/Principal Investigator: Dr Gunar Schirner
Method of Presentation: Poster
The complexity of designing modern embedded-system is increasing at exponential rate. Electronic System level design(ESL) methodology and System Level Design Languages (SLDL) have been introduced to address the complexity in design. ESL focuses on higher abstraction level of design, and SLDL help in capturing the specification. In modern embedded-system the design cost of software content is high as compared to hardware. Nowadays embedded-system software consists of RTOS with multi-threaded application executing on heterogeneous multi-processor systems. Dynamic scheduling behavior, task distribution, priority assignment and latencies of an application executing on RTOS are important non-functional consideration during design space exploration. ESL aids in generation and synthesis of HW/SW models. The software behavior of hardware model form virtual platform . The software generated can be executed on both virtual platform as well as physical hardware. Execution of software on virtual platform allow for profiling and analyzing. This profile data aids in design space exploration. We introduce support for commonly used RTOS, RTEMS into ESL for both ARM and Blackfin processor. We use POSIX standard for interfacing the generated software to RTEMS. Using POSIX standard allows future integration of POSIX compliant operating systems into ESL. We demonstrate the flexibility by synthesizing a H264 decoder along with RTEMS on both ARM and Blackfin processors. We explore the design space by synthesizing a H264 decoder along with uCos-II on ARM processor.