Application-Specific Power-Efficient Approach for Reducing Register File Vulnerability
Lead Presenter: Hamed Tabkhi
Additional Presenters: Prof. Gunar Schirner
Faculty Advisor/Principal Investigator: Prof. Gunar Schirner
Method of Presentation: Poster
With shrinking feature size, embedded processors are becoming more susceptible to soft errors. Investigations show that Register File (RF) has a significant contribution to embedded processors reliability. At the same time, RF already is one of the main hot spots, thus the conventional approaches, such as Error Correction Codes (ECC), are not suitable due to high power overhead. This paper introduces a power efficient approach for improving reliability of heterogeneous register files in embedded processors. The approach is based on the fact that control applications have high demands in reliability, while many special-purpose register are unused in a considerable portion of execution. The paper proposes a static application binary analysis which is applied at function-level granularity and offers a systematic way to manage the RF’s protection by mirroring the content of used registers into unused ones. The simulation results on an enhanced Blackfin processor demonstrate that Register File Vulnerability Factor (RFVF) is reduced from 35% to 6.9% in cost of 1% performance lost on average for control applications from Mibench suite.