Application of Graphene to Transistors: CVD Growth, Nanoribbon Formation, and Electrical PropertiesWhen: Tuesday, August 07, 2012 at 2:00 pm
Where: EG 206
Speaker: Shintaro Sato, PhD
Organization: Green Nanoelectronics Research Center (GNC)
Sponsor: NU Mechanical and Industrial Engineering Colloquium Series
Graphene, a two-dimensional honeycomb carbon lattice, is considered to be a promising material for future electronics devices due to its excellent properties. We actually try to use graphene as a transistor channel and interconnect for future large scale integrated circuits (LSIs). In this talk, we explain our recent progress in its transistor application. In the first part, we demonstrate graphene growth all over a 200-mm or a 300-mm wafer by chemical vapor deposition using Cu film as a catalyst [1, 2]. We explain how the grain size and orientation of graphene are affected by various growth parameters. Electrical properties depending on the grain structures are also described. In the second part, we describe self-organizing formation of graphene ribbons on a Cu/SiO2/Si substrate. In fact, we have found that graphene ribbons can be formed selectively on narrow twin crystal regions with a (001) or high-index surface sandwiched between Cu crystals having (111) surfaces by CVD . In the last part, we explain our recent results on patterning of graphene nanoribbons (GNRs) by Helium Ion Microscope and the on-off operation of a GNR transistor thus fabricated . A new device concept using a GNR is also proposed and demonstrated .
This work was suported by JSP through the “FIRST Program,” initiated by CSTP, Japan. This work was partly conducted at the Nano-Processing Facility supported by ICAN, AIST, Japan.
 S. Sato, et al. ECS Trans. 35(3), 219 (2011)
 S. Sato, et al. ECS Trans. 37(1), 121 (2011)
 K. Hayashi, et al. J. Am. Chem. Soc. dx.doi.org/10.1021/ja300811p
 S. Nakaharai, et al. Extended Abstracts of the 2011 SSDM, Nagoya, 1300 (2011)
 S. Nakaharai, et al. Appl. Phys. Express 5, 015101 (2012)