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"A Joint SW/HW Approach for Reducing Register File Vulnerability",
ACM Transactions on Architecture and Code Optimization (ACM TACO), 02/2015, In Press.
"Alleviating Scalability Limitation of Accelerator-based Platforms",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2018.
"Studying Inter-Warp Divergence Aware Execution on GPUs",
Computer Architecture Letters, 2015.
"Conceptual Abstraction Levels (CALs) for Managing Design Complexity of Market-Oriented MPSoCs",
Elsevier Journal of Microprocessors and Microsystems, 2015.
"Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications",
Springer Journal of Signal Processing and Systems, 2015.
"A Power-efficient Real-time Solution for Adaptive Vision",
IET Computers & Digital Techniques, 2014.
"Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs",
IEEE Embedded Systems Letters (accepted 5/20/14), 05/2014.
"Application-Guided Power Gating Reducing Register File Static Power",
IEEE Transactions on Very Large Scale Integration (TVLSI), 2014.
"A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips",
Microprocessors and Microsystems - Embedded Hardware Design, vol/lev. 35, pp. 766-778, 2011.
"Revisiting Accelerator-Based CMPs: Challenges and Solutions",
Design Automation Conference (DAC), San Francisco, Design Automation Conference (DAC), 06/2015, In Press.
"DS-DSE: Domain-Specific Design Space Exploration for Streaming Applications",
Design Automation and Test in Europe (DATE), Dresden, Germany, DATE, 03/2018.
"OpenCL-based optimizations for acceleration of object tracking on FPGAs and GPUs",
International Workshop on Architectures and Systems for Real-time Mobile Vision Applications (ASR-MOV), Barcelona, Spain, 03/2016.
"Guiding Power/Quality Exploration for Communication-Intense Stream Processing",
Great Lakes Symposium on VLSI (GLS-VLSI), Boston (MA), US, 05/2016.
"Hardware thread reordering to boost OpenCL throughput on FPGAs",
ICCD, Phoenix (AZ), International Conference on Computer Design, 2016.
Improving Scalability of CMPs with Dense ACCs Coverage
, Dresden, Germany, DATE, 2016.
"Taming the Memory Demand Complexity of Adaptive Vision Algorithms",
IESS, Foz do Iguacu, 2015.
"An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction",
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAPs), Toronto, Canada, 2015.
Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA
, Boston, MA, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2015.
"A GPU-based Algorithm-specific Optimization for High-performance Background Subtraction",
International Conference on Parallel Processing, Minneapolis, MN, 2014.
"Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs",
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, 2014.
"A Novel Quantitative ESL Based SOC Architecture Exploration Methodology",
Analog Devices General Technical Conference (ADI GTC), April, 2013.
"Flexible Function-Level Acceleration of Embedded Vision Applications using the Pipelined Vision",
Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), 11/2013.
"Algorithm and Architecture Co-Design of Mixture of Gaussian (MoG) Background Subtraction for Embedded Vision Processor",
Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), 11/2013.
"ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors",
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2012.
"AFReP: Application-guided Function-level Registerfile power-gating for embedded processors",
International Conference on Computer-Aided Design (ICCAD), 2012.
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