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2013
A. Agarwal, "Integrating Instruction Set Simulator into a System Level Design Environment", Electrical and Computer Engineering, vol/lev. MSc, Boston, Northeastern , 02/2013.
2011
S. Abdi, Y. Hwang, L. Yu, G. Schirner and D. D. Gajski, "Automatic TLM Generation for Early Validation of Multicore Systems", IEEE Design and Test of Computers, vol/lev. 28, pp. 10-19, 2011.
2010
Y. Hwang, G. Schirner, S. Abdi and D. D. Gajski, "Accurate Timed RTOS Model for Transaction Level Modeling", Proceedings of Design Automation and Test in Europe (DATE), Dresden, Germany, 2010.
2009
Y. Hwang, G. Schirner and S. Abdi, "Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support", Analysis, Architectures and Modelling of Embedded Systems, Springer Berlin Heidelberg, 2009.
Y. Hwang, G. Schirner and S. Abdi, "Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support", Analysis, Architectures and Modelling of Embedded Systems, Springer Berlin Heidelberg, 2009.
D. D. Gajski, S. Abdi, A. Gerstlauer and G. Schirner, Embedded System Design: Modeling, Synthesis and Verification , 2009.
S. Abdi, G. Schirner, I. Viskic, H. Cho, Y. Hwang, L. Yu and D. D. Gajski, "Hardware-dependent Software synthesis for many-core embedded systems", In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 01/2009.

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