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N. Teimouri, "Improving Scalability of Chip-MultiProcessors with Many HW ACCelerators", Electrical and Computer Engineering, Boston, Northeastern University, 12/2017.
K. Moazzami, "Calibrative Source-level Multi-target Performance Estimation", Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
H. Tabkhi, "High-Performance Power-Efficient Solutions for embedded vision", Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
H. Qiu, "Managing bulk sensor data for heterogeneous distributed systems", Electrical and Computer Engineering, vol/lev. MSc, Boston, Northeastern, 04/2014.
J. Zhang, "Integration of Algorithm-Level Design and System-Level Design: Synthesis, Optimization and Exploration", Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
E. Llamos, "Analysis and Visualization of Communication/Computation Patterns of High-Performance Applications", Electrical and Computer Engineering, vol/lev. MSc, Boston, Northeastern, 12/2013.
A. Agarwal, "Integrating Instruction Set Simulator into a System Level Design Environment", Electrical and Computer Engineering, vol/lev. MSc, Boston, Northeastern , 02/2013.
R. Kangralkar, "Enhancing a System-Level Design Flow by RTOS Integration", Electrical and Computer Engineering, vol/lev. Master of Science, Boston, Massachusetts, Northeastern University, pp. 93, 07/2012.
G. Schirner, "Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design", Electrical Engineering and Computer Science, vol/lev. PhD, Irvine, CA, University of California, Irvine, 04/2008.
G. Schirner, "System Level Modeling of an AMBA Bus", Electrical Engineering and Computer Science, vol/lev. MS, Irvine, CA, University of California, Irvine, 2005.

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