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Export 25 results:
[ Author
] Keyword Title Type Year Filters: First Letter Of Last Name is T [Clear All Filters]
A Power-efficient FPGA-based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution
, FCCM, 2014.
"Application-specific power-efficient approach for reducing register file vulnerability",
Design Automation and Test In Europe (DATE), 2012.
"A Power-efficient Real-time Solution for Adaptive Vision",
IET Computers & Digital Techniques, 2014.
"Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications",
Springer Journal of Signal Processing and Systems, 2015.
"Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs",
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, 2014.
"ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors",
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2012.
"High-Performance Power-Efficient Solutions for embedded vision",
Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
"Conceptual Abstraction Levels (CALs) for Managing Design Complexity of Market-Oriented MPSoCs",
Elsevier Journal of Microprocessors and Microsystems, 2015.
"Application-Guided Power Gating Reducing Register File Static Power",
IEEE Transactions on Very Large Scale Integration (TVLSI), 2014.
"An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction",
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAPs), Toronto, Canada, 2015.
"An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors",
IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 10/2008.
Guiding Power/Quality Exploration for Communication-Intense Stream Processing
, San Francisco, USA, 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 06/2014.
High-Performance Power-Efficient Solutions for Embedded Vision Computing
, San Francisco, DAC 2015, 2015.
"Algorithm and Architecture Co-Design of Mixture of Gaussian (MoG) Background Subtraction for Embedded Vision Processor",
Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), 11/2013.
"Guiding Power/Quality Exploration for Communication-Intense Stream Processing",
Great Lakes Symposium on VLSI (GLS-VLSI), Boston (MA), US, 05/2016.
"Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs",
IEEE Embedded Systems Letters (accepted 5/20/14), 05/2014.
"AFReP: Application-guided Function-level Registerfile power-gating for embedded processors",
International Conference on Computer-Aided Design (ICCAD), 2012.
"A Joint SW/HW Approach for Reducing Register File Vulnerability",
ACM Transactions on Architecture and Code Optimization (ACM TACO), 02/2015, In Press.
"Simultaneous hardware and time redundancy with online task scheduling for low energy highly reliable standby-sparing system",
{ACM} Trans. Embedded Comput. Syst., vol/lev. 13, pp. 86:1–86:31, 2014.
"Power and Performance Efficient Partial Circuits in Packet-Switched Networks-on-Chip",
21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, {PDP} 2013, Belfast, United Kingdom, February 27 - March 1, 2013, 2013.
"Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths",
Architecture of Computing Systems - {ARCS} 2011 - 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings, 2011.
"Alleviating Scalability Limitation of Accelerator-based Platforms",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2018.
"Improving Scalability of Chip-MultiProcessors with Many HW ACCelerators",
Electrical and Computer Engineering, Boston, Northeastern University, 12/2017.
"Revisiting Accelerator-Based CMPs: Challenges and Solutions",
Design Automation Conference (DAC), San Francisco, Design Automation Conference (DAC), 06/2015, In Press.
Improving Scalability of CMPs with Dense ACCs Coverage
, Dresden, Germany, DATE, 2016.
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