You are here

Export 18 results:
[ Author(Asc)] Keyword Title Type Year
Filters: First Letter Of Last Name is T and Author is Hamed Tabkhi  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
T
H. Tabkhi, G. S Miremadi and E. A, "An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors", IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 10/2008.
H. Tabkhi and G. Schirner, "ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2012.
H. Tabkhi and G. Schirner, "Application-specific power-efficient approach for reducing register file vulnerability", Design Automation and Test In Europe (DATE), 2012.
H. Tabkhi and G. Schirner, "AFReP: Application-guided Function-level Registerfile power-gating for embedded processors", International Conference on Computer-Aided Design (ICCAD), 2012.
H. Tabkhi, R. Bushey and G. Schirner, "Algorithm and Architecture Co-Design of Mixture of Gaussian (MoG) Background Subtraction for Embedded Vision Processor", Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), 11/2013.
H. Tabkhi and G. Schirner, "Application-Guided Power Gating Reducing Register File Static Power", IEEE Transactions on Very Large Scale Integration (TVLSI), 2014.
H. Tabkhi, R. Bushey and G. Schirner, "Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs", IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, 2014.
H. Tabkhi, M. Sabbagh and G. Schirner, A Power-efficient FPGA-based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution , FCCM, 2014.
H. Tabkhi, R. Bushey and G. Schirner, "Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs", IEEE Embedded Systems Letters (accepted 5/20/14), 05/2014.
H. Tabkhi, M. Sabbagh and G. Schirner, Guiding Power/Quality Exploration for Communication-Intense Stream Processing , San Francisco, USA, 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 06/2014.
H. Tabkhi, "High-Performance Power-Efficient Solutions for embedded vision", Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
H. Tabkhi, M. Sabbagh and G. Schirner, "A Power-efficient Real-time Solution for Adaptive Vision", IET Computers & Digital Techniques, 2014.
H. Tabkhi and G. Schirner, "A Joint SW/HW Approach for Reducing Register File Vulnerability", ACM Transactions on Architecture and Code Optimization (ACM TACO), 02/2015, In Press.
H. Tabkhi, M. Sabbagh and G. Schirner, "An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction", IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAPs), Toronto, Canada, 2015.
H. Tabkhi, High-Performance Power-Efficient Solutions for Embedded Vision Computing , San Francisco, DAC 2015, 2015.
H. Tabkhi, R. Bushey and G. Schirner, "Conceptual Abstraction Levels (CALs) for Managing Design Complexity of Market-Oriented MPSoCs", Elsevier Journal of Microprocessors and Microsystems, 2015.
H. Tabkhi, R. Bushey and G. Schirner, "Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications", Springer Journal of Signal Processing and Systems, 2015.
H. Tabkhi, M. Sabbagh and G. Schirner, "Guiding Power/Quality Exploration for Communication-Intense Stream Processing", Great Lakes Symposium on VLSI (GLS-VLSI), Boston (MA), US, 05/2016.

Theme by Danetsoft and Danang Probo Sayekti inspired by Maksimer