- Home
- Members
- Research
- Publications
- Classes
- Current Classes
- Past Classes
- EECE 7368- Fall 2015
- EECE2160 36762 - Spring 2015
- EECE2160 16726 - Fall 2014
- EECE 4534 - Spring 2014
- EECE 7368- Fall 2013
- EECE4534 - Spring 2013
- EECE 7368 - Fall 2012
- EECE 4534 - Spring 2012
- EECE 7368 - Fall 2011
- EECE 4534 - Spring 2011
- EECE 7368 - Fall 2010
- EECE 4534 - Spring 2010
- EECE 4534 - Fall 2009
- Microprocessor-based Design (Spring 2016)
- Embedded Systems Classes
- Resources
- Activities
- Nasibeh Teimouri's PhD defense
- Adorable Sophie Schirner's arrival
- Dr. Hamed Tabkhi, goodbye celebration
- Group gathering, Fall 2015
- Group Luncheons, Fall 2015
- Esl members at DAC 2015
- Group Luncheons, Spring 2015
- Group Luncheons, Winter 2015
- Group Luncheons, Fall 2014
- Graduation party on Salisbury beach state
- Group Luncheons, summer 2014
- Group outing, Summer 2014
- Semester Wrap-up, spring 2014
- Group Luncheons, 2013
- Group outing, Fall 2013
- Contact ESL
You are here
Export 35 results:
Author Keyword Title Type [ Year
] Filters: Author is Hamed Tabkhi [Clear All Filters]
"A Joint SW/HW Approach for Reducing Register File Vulnerability",
ACM Transactions on Architecture and Code Optimization (ACM TACO), 02/2015, In Press.
"Revisiting Accelerator-Based CMPs: Challenges and Solutions",
Design Automation Conference (DAC), San Francisco, Design Automation Conference (DAC), 06/2015, In Press.
"Alleviating Scalability Limitation of Accelerator-based Platforms",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2018.
"DS-DSE: Domain-Specific Design Space Exploration for Streaming Applications",
Design Automation and Test in Europe (DATE), Dresden, Germany, DATE, 03/2018.
"Guiding Power/Quality Exploration for Communication-Intense Stream Processing",
Great Lakes Symposium on VLSI (GLS-VLSI), Boston (MA), US, 05/2016.
"Hardware thread reordering to boost OpenCL throughput on FPGAs",
ICCD, Phoenix (AZ), International Conference on Computer Design, 2016.
Improving Scalability of CMPs with Dense ACCs Coverage
, Dresden, Germany, DATE, 2016.
"OpenCL-based optimizations for acceleration of object tracking on FPGAs and GPUs",
International Workshop on Architectures and Systems for Real-time Mobile Vision Applications (ASR-MOV), Barcelona, Spain, 03/2016.
"Bridging Architecture and Programming for Throughput-Oriented Vision Processing",
International Symposium on Field-Programmable Gate Arrays (FPGA), 02/2015.
"Conceptual Abstraction Levels (CALs) for Managing Design Complexity of Market-Oriented MPSoCs",
Elsevier Journal of Microprocessors and Microsystems, 2015.
"An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction",
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAPs), Toronto, Canada, 2015.
Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA
, Boston, MA, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2015.
"Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications",
Springer Journal of Signal Processing and Systems, 2015.
High-Performance Power-Efficient Solutions for Embedded Vision Computing
, San Francisco, DAC 2015, 2015.
"Studying Inter-Warp Divergence Aware Execution on GPUs",
Computer Architecture Letters, 2015.
"Taming the Memory Demand Complexity of Adaptive Vision Algorithms",
IESS, Foz do Iguacu, 2015.
"Application-Guided Power Gating Reducing Register File Static Power",
IEEE Transactions on Very Large Scale Integration (TVLSI), 2014.
"Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs",
IEEE Embedded Systems Letters (accepted 5/20/14), 05/2014.
"Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs",
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, 2014.
"A GPU-based Algorithm-specific Optimization for High-performance Background Subtraction",
International Conference on Parallel Processing, Minneapolis, MN, 2014.
Guiding Power/Quality Exploration for Communication-Intense Stream Processing
, San Francisco, USA, 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 06/2014.
"High-Performance Power-Efficient Solutions for embedded vision",
Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
A Power-efficient FPGA-based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution
, FCCM, 2014.
"A Power-efficient Real-time Solution for Adaptive Vision",
IET Computers & Digital Techniques, 2014.
"Algorithm and Architecture Co-Design of Mixture of Gaussian (MoG) Background Subtraction for Embedded Vision Processor",
Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), 11/2013.
Pages
Theme by Danetsoft and Danang Probo Sayekti inspired by Maksimer