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Export 35 results:
Author Keyword [ Title
] Type Year Filters: Author is Hamed Tabkhi [Clear All Filters]
"AFReP: Application-guided Function-level Registerfile power-gating for embedded processors",
International Conference on Computer-Aided Design (ICCAD), 2012.
"Algorithm and Architecture Co-Design of Mixture of Gaussian (MoG) Background Subtraction for Embedded Vision Processor",
Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), 11/2013.
"Alleviating Scalability Limitation of Accelerator-based Platforms",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2018.
"Application-Guided Power Gating Reducing Register File Static Power",
IEEE Transactions on Very Large Scale Integration (TVLSI), 2014.
"Application-specific power-efficient approach for reducing register file vulnerability",
Design Automation and Test In Europe (DATE), 2012.
"ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors",
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2012.
"An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors",
IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 10/2008.
"Bridging Architecture and Programming for Throughput-Oriented Vision Processing",
International Symposium on Field-Programmable Gate Arrays (FPGA), 02/2015.
"Conceptual Abstraction Levels (CALs) for Managing Design Complexity of Market-Oriented MPSoCs",
Elsevier Journal of Microprocessors and Microsystems, 2015.
"A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic",
ICM International Conference on Microelectronics, 12/2008.
"DS-DSE: Domain-Specific Design Space Exploration for Streaming Applications",
Design Automation and Test in Europe (DATE), Dresden, Germany, DATE, 03/2018.
"An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction",
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAPs), Toronto, Canada, 2015.
"An Efficient Method to Reliable Data Transmission in Network-on-Chips",
13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), 09/2010.
Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA
, Boston, MA, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2015.
"Flexible Function-Level Acceleration of Embedded Vision Applications using the Pipelined Vision",
Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), 11/2013.
"Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs",
IEEE Embedded Systems Letters (accepted 5/20/14), 05/2014.
"Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications",
Springer Journal of Signal Processing and Systems, 2015.
"Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs",
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, 2014.
"A GPU-based Algorithm-specific Optimization for High-performance Background Subtraction",
International Conference on Parallel Processing, Minneapolis, MN, 2014.
"Guiding Power/Quality Exploration for Communication-Intense Stream Processing",
Great Lakes Symposium on VLSI (GLS-VLSI), Boston (MA), US, 05/2016.
Guiding Power/Quality Exploration for Communication-Intense Stream Processing
, San Francisco, USA, 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 06/2014.
"Hardware thread reordering to boost OpenCL throughput on FPGAs",
ICCD, Phoenix (AZ), International Conference on Computer Design, 2016.
"High-Performance Power-Efficient Solutions for embedded vision",
Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
High-Performance Power-Efficient Solutions for Embedded Vision Computing
, San Francisco, DAC 2015, 2015.
Improving Scalability of CMPs with Dense ACCs Coverage
, Dresden, Germany, DATE, 2016.
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