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Export 8 results:
Author Keyword Title [ Type
] Year Filters: Author is Nasibeh Teimouri [Clear All Filters]
"Improving Scalability of Chip-MultiProcessors with Many HW ACCelerators",
Electrical and Computer Engineering, Boston, Northeastern University, 12/2017.
"Revisiting Accelerator-Based CMPs: Challenges and Solutions",
Design Automation Conference (DAC), San Francisco, Design Automation Conference (DAC), 06/2015, In Press.
Improving Scalability of CMPs with Dense ACCs Coverage
, Dresden, Germany, DATE, 2016.
"Modeling and Analysis of SLDL-captured NoC Abstractions",
IESS, Foz do Iguacu, Brazil, 2015.
"Power and Performance Efficient Partial Circuits in Packet-Switched Networks-on-Chip",
21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, {PDP} 2013, Belfast, United Kingdom, February 27 - March 1, 2013, 2013.
"Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths",
Architecture of Computing Systems - {ARCS} 2011 - 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings, 2011.
"Alleviating Scalability Limitation of Accelerator-based Platforms",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2018.
"Simultaneous hardware and time redundancy with online task scheduling for low energy highly reliable standby-sparing system",
{ACM} Trans. Embedded Comput. Syst., vol/lev. 13, pp. 86:1–86:31, 2014.
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