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Export 129 results:
Author Keyword Title Type [ Year
] Filters: First Letter Of Last Name is S [Clear All Filters]
"An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction",
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAPs), Toronto, Canada, 2015.
"An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction",
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAPs), Toronto, Canada, 2015.
"Engaging Sophomores in Embedded Design using Robotics",
Workshop on Computer Architecture Education, Portland, OR, 06/2015.
Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA
, Boston, MA, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2015.
"Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications",
Springer Journal of Signal Processing and Systems, 2015.
"Modeling and Analysis of SLDL-captured NoC Abstractions",
IESS, Foz do Iguacu, Brazil, 2015.
"Optimization of Energy Efficient Relay Position for Galvanic Coupled Intra-body Communication",
IEEE WCNC, 2015.
"Optimization of Energy Efficient Relay Position for Galvanic Coupled Intra-body Communication",
IEEE WCNC, 2015.
"Rapid Heterogeneous Prototyping From Simulink",
International Symposium on Quality Electronic Design (ISQED), 03/2015.
"Rapid, High-Level Performance Estimation for DSE using Calibrated Weight Tables",
IESS, Foz do Iguacu, Brazil, 2015.
"Reducing Dynamic Dispatch Overhead (DDO) of SLDL-Synthesized Embedded Software",
Asia and South Pacific Design Automation Conference (ASPDAC), Chiba/Tokyo, Japan, 2015.
"Studying Inter-Warp Divergence Aware Execution on GPUs",
Computer Architecture Letters, 2015.
"Taming the Memory Demand Complexity of Adaptive Vision Algorithms",
IESS, Foz do Iguacu, 2015.
"Taming the Memory Demand Complexity of Adaptive Vision Algorithms",
IESS, Foz do Iguacu, 2015.
"Towards Closing the Specification Gap by Integrating Algorithm-Level and System-Level Design",
Springer Design Automation for Embedded Systems (DAEM), 2015.
"An Embedded Device for Brain/Body Signal Acquisition and Processing",
International Symposium on Rapid System Prototyping (RSP), Pittsburgh, PA, 2016.
Framework for Rapid Development of Embedded Human-in-the-Loop Cyber-Physical Systems
, International Conference on BioInformatics and BioEngineering, 2016.
"Guiding Power/Quality Exploration for Communication-Intense Stream Processing",
Great Lakes Symposium on VLSI (GLS-VLSI), Boston (MA), US, 05/2016.
"Guiding Power/Quality Exploration for Communication-Intense Stream Processing",
Great Lakes Symposium on VLSI (GLS-VLSI), Boston (MA), US, 05/2016.
"Hardware thread reordering to boost OpenCL throughput on FPGAs",
ICCD, Phoenix (AZ), International Conference on Computer Design, 2016.
Improving Scalability of CMPs with Dense ACCs Coverage
, Dresden, Germany, DATE, 2016.
"OpenCL-based optimizations for acceleration of object tracking on FPGAs and GPUs",
International Workshop on Architectures and Systems for Real-time Mobile Vision Applications (ASR-MOV), Barcelona, Spain, 03/2016.
"Alleviating Scalability Limitation of Accelerator-based Platforms",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2018.
"DS-DSE: Domain-Specific Design Space Exploration for Streaming Applications",
Design Automation and Test in Europe (DATE), Dresden, Germany, DATE, 03/2018.
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