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G. Schirner, "Hardware/Software Co-Design: System Synthesis Using MATLAB and Simulink", Mathworks, Natick, MA, 04/2012.
G. Schirner, A. Gerstlauer and R. Dömer, "Fast and Accurate Processor Models for efficient MPSoC Design", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol/lev. 15, pp. 10:1-10:26, 02/2010.
G. Schirner, T. Harmon and R. Klefstad, "Late Demarshalling: A Technique for Efficient Multi-language Middleware for Embedded Systems", Proceedings of the International symposium on Distributed Objects and Applications (DOA), Larnaca, Cyprus, 10/2004.
G. Schirner, D. D. Gajski and S. Abdi, "Requirements and Specification for Multi-Core SW Synthesis", Technical Report TR-08-16, CECS, UC Irvine, 12/2008.
G. Schirner and R. Dömer, "Abstract Communication Modeling: A Case Study Using the CAN Automotive Bus", From Specification to Embedded Systems Application, Manaus, Brazil, Springer, 08/2005.
G. Schirner, S. Feng and D. Erdogmus, Rapid Embedded Realization of Brain Computer Interfacing Applications , INV-14090 , 04/2014.
M. Swaminathan, J. Sebastià Pujol and G. Schirner, "Multi-path 2-Port Channel Characterization for Galvanic Coupled Intra-body Communication", BodyNets, London UK, International Conference on Body Area Networks, 09/2014.
M.. Swaminathan, F.. S. Cabrera, J.. S. Pujol, U.. Muncuk, G. Schirner and K. Chowdhury, "Multi-path Model and Sensitivity Analysis for Galvanic Coupled Intra-body Communication through Layered Tissue", IEEE Transactions on Biomedical Circuits and Systems, 05/2015, In Press.
M.. Swaminathan, G. Schirner and K. Chowdhury, "Optimization of Energy Efficient Relay Position for Galvanic Coupled Intra-body Communication", IEEE WCNC, 2015.
T
H. Tabkhi and G. Schirner, "ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2012.
H. Tabkhi, R. Bushey and G. Schirner, "Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications", Springer Journal of Signal Processing and Systems, 2015.
H. Tabkhi, R. Bushey and G. Schirner, "Algorithm and Architecture Co-Design of Mixture of Gaussian (MoG) Background Subtraction for Embedded Vision Processor", Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), 11/2013.
H. Tabkhi, R. Bushey and G. Schirner, "Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs", IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, 2014.
H. Tabkhi and G. Schirner, "A Joint SW/HW Approach for Reducing Register File Vulnerability", ACM Transactions on Architecture and Code Optimization (ACM TACO), 02/2015, In Press.
H. Tabkhi and G. Schirner, "Application-Guided Power Gating Reducing Register File Static Power", IEEE Transactions on Very Large Scale Integration (TVLSI), 2014.
H. Tabkhi, R. Bushey and G. Schirner, "Conceptual Abstraction Levels (CALs) for Managing Design Complexity of Market-Oriented MPSoCs", Elsevier Journal of Microprocessors and Microsystems, 2015.
H. Tabkhi, M. Sabbagh and G. Schirner, "A Power-efficient Real-time Solution for Adaptive Vision", IET Computers & Digital Techniques, 2014.
H. Tabkhi and G. Schirner, "AFReP: Application-guided Function-level Registerfile power-gating for embedded processors", International Conference on Computer-Aided Design (ICCAD), 2012.
H. Tabkhi, "High-Performance Power-Efficient Solutions for embedded vision", Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
H. Tabkhi, M. Sabbagh and G. Schirner, Guiding Power/Quality Exploration for Communication-Intense Stream Processing , San Francisco, USA, 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 06/2014.
H. Tabkhi and G. Schirner, "Application-specific power-efficient approach for reducing register file vulnerability", Design Automation and Test In Europe (DATE), 2012.
H. Tabkhi, M. Sabbagh and G. Schirner, A Power-efficient FPGA-based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution , FCCM, 2014.
H. Tabkhi, M. Sabbagh and G. Schirner, "An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction", IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAPs), Toronto, Canada, 2015.
H. Tabkhi, G. S Miremadi and E. A, "An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors", IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 10/2008.
H. Tabkhi, R. Bushey and G. Schirner, "Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs", IEEE Embedded Systems Letters (accepted 5/20/14), 05/2014.

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