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Export 107 results:
Author Keyword Title Type [ Year
] Filters: Author is Gunar Schirner [Clear All Filters]
"Hardware-dependent Software synthesis for many-core embedded systems",
In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 01/2009.
"High-Level Development, Modeling and Automatic Generation of Hardware-Dependent Software",
Hardware-dependent Software, Springer Netherlands, pp. 203-231, 2009.
"Real-Time MP3 Decoding on FPGA: a Case Study of System Model Features,",
Technical Report TR 09-09, CECS, UC Irvine, 07/2009.
"Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design",
Electrical Engineering and Computer Science, vol/lev. PhD, Irvine, CA, University of California, Irvine, 04/2008.
"Automatic Generation of Hardware dependent Software for MPSoCs from Abstract System Specifications",
Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, 11/2008.
"Efficient Embedded System Models Using Result Oriented Modeling",
University of York, York, England, 09/2008.
"Efficient Embedded System Models Using Result Oriented Modeling",
Offis, University of Oldenburg, Oldenburg, Germany, 09/2008.
"Efficient Embedded System Models Using Result Oriented Modeling",
C-LAB, University of Paderborn, Germany, 09/2008.
"Embedded System Environment (Front End) ESE Version 2.0 Evaluation Tutorial",
TR 08-15, CECS, UC Irvine, 12/2008.
"Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling",
In Proceedings of Design Automation and Test in Europe (DATE), Munich, Germany, 03, 2008.
"Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling",
ACM Transactions on Embedded Computer Systems, vol/lev. 8, pp. 4:1-4:29, 12/2008.
"Requirements and Specification for Multi-Core SW Synthesis",
Technical Report TR-08-16, CECS, UC Irvine, 12/2008.
"Timed RTOS Models in Automatically Generated Cycle-Approximate TLMs",
TR-08-12, CECS, UC Irvine, 09/2008.
"Abstract, Multifaceted Modeling of Embedded Processors for System Level Design",
Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 01/2007.
Analysis and Optimization of Fast and Accurate SoC Platform Models
, San Diego, California, In SIGDA PhD Forum at the Design Automation Conference (DAC), 2007.
"Embedded Software Development in an System-Level Design Flow: Case Study for an ARM Processor",
Proceedings of the International Embedded Systems Symposium, Irvine, CA, 06/2007.
"Improving Accuracy of Transaction Level Models in Multi-Processor System-on-Chip Design",
Embedded System Design , University of Dortmund, Germany, 12/2007.
"Result Oriented Modeling a Novel Technique for Fast and Accurate TLM",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol/lev. 26, pp. 1688-1699, 09/2007.
"Accurate yet Fast Modeling of Real-Time Communication",
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES ISSS), Seoul, Korea, 10/2006.
"Fast and Accurate Transaction Level Models using Result Oriented Modeling",
In Proceedings of the International Conference on Computer Aided Design (ICCAD), San Jose, CA, 11/2006.
"Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor",
TR 06-06, CECS, UC Irvine, 04/2006.
"Necessary and Sufficient Functionality and Parameters for SoC Communication",
TR-06-01, 05/2006.
"Quantitative Analysis of Transaction Level Models for the AMBA Bus",
Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, 03/2006.
"System-On-Chip Component Models",
TR-06-10, CECS, UC Irvine, 05/2006.
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