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] Type Year Filters: Author is Gunar Schirner [Clear All Filters]
Embedded Systems Laboratory (ESL) Research Overview
, Boston, MA, Mathworks Research Faculty Summit, 06/2014.
Embedded Systems: Design, Analysis and Verification
, vol/lev. 403, Springer, 2013.
"Embedded System Environment (Front End) ESE Version 2.0 Evaluation Tutorial",
TR 08-15, CECS, UC Irvine, 12/2008.
"Embedded Software Development in an System-Level Design Flow: Case Study for an ARM Processor",
Proceedings of the International Embedded Systems Symposium, Irvine, CA, 06/2007.
"An Embedded Device for Brain/Body Signal Acquisition and Processing",
International Symposium on Rapid System Prototyping (RSP), Pittsburgh, PA, 2016.
"Efficient Embedded System Models Using Result Oriented Modeling",
University of York, York, England, 09/2008.
"Efficient Embedded System Models Using Result Oriented Modeling",
C-LAB, University of Paderborn, Germany, 09/2008.
"Efficient Embedded System Models Using Result Oriented Modeling",
Offis, University of Oldenburg, Oldenburg, Germany, 09/2008.
"An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction",
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAPs), Toronto, Canada, 2015.
"DS-DSE: Domain-Specific Design Space Exploration for Streaming Applications",
Design Automation and Test in Europe (DATE), Dresden, Germany, DATE, 03/2018.
Demand-Driven Granularity Tuning In Specification Synthesis
, San Francisco, USA, 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 06/2014.
"CORBA in Telecommunication Products",
half-day tutorial with Antonio Fontan, Alcatel USA (aud.: 45 system designers and SW engineers), Petaluma, CA, 04/2002.
"Conceptual Abstraction Levels (CALs) for Managing Design Complexity of Market-Oriented MPSoCs",
Elsevier Journal of Microprocessors and Microsystems, 2015.
"Bridging Architecture and Programming for Throughput-Oriented Vision Processing",
International Symposium on Field-Programmable Gate Arrays (FPGA), 02/2015.
"Automatic TLM Generation for Early Validation of Multicore Systems",
IEEE Design and Test of Computers, vol/lev. 28, pp. 10-19, 2011.
"Automatic Specification Granularity Tuning for Design Space Exploration",
Proceedings of the ACM/IEEE Conference on Design, Automation & Test in Europe (DATE), Dresden, Germany, 03/2014.
"Automatic Generation of Hardware dependent Software for MPSoCs from Abstract System Specifications",
Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, 11/2008.
"Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support",
Analysis, Architectures and Modelling of Embedded Systems, Springer Berlin Heidelberg, 2009.
"ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors",
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2012.
"Application-specific power-efficient approach for reducing register file vulnerability",
Design Automation and Test In Europe (DATE), 2012.
"Application-Guided Power Gating Reducing Register File Static Power",
IEEE Transactions on Very Large Scale Integration (TVLSI), 2014.
"Analyzing Power Efficiency of Optimization Techniques and Algorithm Design Methods for Applications on Heterogeneous Platforms",
International Journal of High Performance Computing Applications (IJHPCA), 2014.
"Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design",
Electrical Engineering and Computer Science, vol/lev. PhD, Irvine, CA, University of California, Irvine, 04/2008.
Analysis and Optimization of Fast and Accurate SoC Platform Models
, San Diego, California, In SIGDA PhD Forum at the Design Automation Conference (DAC), 2007.
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