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Author Keyword Title [ Type(Asc)] Year
Conference Paper
G. Schirner and R. Dömer, Analysis and Optimization of Fast and Accurate SoC Platform Models , San Diego, California, In SIGDA PhD Forum at the Design Automation Conference (DAC), 2007.
G. Schirner and R. Dömer, "Quantitative Analysis of Transaction Level Models for the AMBA Bus", Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, 03/2006.
G. Schirner and R. Dömer, "Fast and Accurate Transaction Level Models using Result Oriented Modeling", In Proceedings of the International Conference on Computer Aided Design (ICCAD), San Jose, CA, 11/2006.
G. Schirner and R. Dömer, "Accurate yet Fast Modeling of Real-Time Communication", Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES ISSS), Seoul, Korea, 10/2006.
G. Schirner and R. Dömer, "Abstract Communication Modeling: A Case Study Using the CAN Automotive Bus", From Specification to Embedded Systems Application, Manaus, Brazil, Springer, 08/2005.
G. Schirner, T. Harmon and R. Klefstad, "Late Demarshalling: A Technique for Efficient Multi-language Middleware for Embedded Systems", Proceedings of the International symposium on Distributed Objects and Applications (DOA), Larnaca, Cyprus, 10/2004.
Thesis
N. Teimouri, "Improving Scalability of Chip-MultiProcessors with Many HW ACCelerators", Electrical and Computer Engineering, Boston, Northeastern University, 12/2017.
H. Qiu, "Managing bulk sensor data for heterogeneous distributed systems", Electrical and Computer Engineering, vol/lev. MSc, Boston, Northeastern, 04/2014.
H. Tabkhi, "High-Performance Power-Efficient Solutions for embedded vision", Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
J. Zhang, "Integration of Algorithm-Level Design and System-Level Design: Synthesis, Optimization and Exploration", Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
K. Moazzami, "Calibrative Source-level Multi-target Performance Estimation", Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
A. Agarwal, "Integrating Instruction Set Simulator into a System Level Design Environment", Electrical and Computer Engineering, vol/lev. MSc, Boston, Northeastern , 02/2013.
E. Llamos, "Analysis and Visualization of Communication/Computation Patterns of High-Performance Applications", Electrical and Computer Engineering, vol/lev. MSc, Boston, Northeastern, 12/2013.
R. Kangralkar, "Enhancing a System-Level Design Flow by RTOS Integration", Electrical and Computer Engineering, vol/lev. Master of Science, Boston, Massachusetts, Northeastern University, pp. 93, 07/2012.
G. Schirner, "Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design", Electrical Engineering and Computer Science, vol/lev. PhD, Irvine, CA, University of California, Irvine, 04/2008.
G. Schirner, "System Level Modeling of an AMBA Bus", Electrical Engineering and Computer Science, vol/lev. MS, Irvine, CA, University of California, Irvine, 2005.
Report
J.. Zhang, H.. Tabkhi and G.. Schirner, Mitigating Application Diversity for Allocating a Unified ACC-Rich Platform , 2019.
X. Han and G. Schirner, "Real-Time MP3 Decoding on FPGA: a Case Study of System Model Features,", Technical Report TR 09-09, CECS, UC Irvine, 07/2009.
D. D. Gajski, S. Abdi, G. Schirner, H. Cho, Y. Hwang, L. Yu, I. Viskic and Q.-V.. Dnag, "Embedded System Environment (Front End) ESE Version 2.0 Evaluation Tutorial", TR 08-15, CECS, UC Irvine, 12/2008.
G. Schirner, D. D. Gajski and S. Abdi, "Requirements and Specification for Multi-Core SW Synthesis", Technical Report TR-08-16, CECS, UC Irvine, 12/2008.
Y. Hwang, G. Schirner and S. Abdi, "Timed RTOS Models in Automatically Generated Cycle-Approximate TLMs", TR-08-12, CECS, UC Irvine, 09/2008.
G. Schirner, G. Sachdeva, A. Gerstlauer and R. Dömer, "Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor", TR 06-06, CECS, UC Irvine, 04/2006.
A. Gerstlauer, G. Schirner, D. Shin, J. Peng and R. Dömer, "System-On-Chip Component Models", TR-06-10, CECS, UC Irvine, 05/2006.
A. Gerstlauer, G. Schirner, D. Shin and J. Peng, "Necessary and Sufficient Functionality and Parameters for SoC Communication", TR-06-01, 05/2006.
G. Schirner and R. Dömer, "Using Result Oriented Modeling for Fast yet Accurate TLMs", TR-05-05, CECS, UC Irvine, 05/2005.

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