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G. Schirner, A. Gerstlauer and R. Dömer, "Fast and Accurate Processor Models for efficient MPSoC Design", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol/lev. 15, pp. 10:1-10:26, 02/2010.
G. Schirner, T. Harmon and R. Klefstad, "Late Demarshalling: A Technique for Efficient Multi-language Middleware for Embedded Systems", Proceedings of the International symposium on Distributed Objects and Applications (DOA), Larnaca, Cyprus, 10/2004.
G. Schirner, D. D. Gajski and S. Abdi, "Requirements and Specification for Multi-Core SW Synthesis", Technical Report TR-08-16, CECS, UC Irvine, 12/2008.
G. Schirner and R. Dömer, "Abstract Communication Modeling: A Case Study Using the CAN Automotive Bus", From Specification to Embedded Systems Application, Manaus, Brazil, Springer, 08/2005.
G. Schirner, S. Feng and D. Erdogmus, Rapid Embedded Realization of Brain Computer Interfacing Applications , INV-14090 , 04/2014.
G. Schirner, "Efficient Embedded System Models Using Result Oriented Modeling", Offis, University of Oldenburg, Oldenburg, Germany, 09/2008.
G. Schirner, "CORBA in Telecommunication Products", half-day tutorial with Antonio Fontan, Alcatel USA (aud.: 45 system designers and SW engineers), Petaluma, CA, 04/2002.
G. Schirner and R. Dömer, "Quantitative Analysis of Transaction Level Models for the AMBA Bus", Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, 03/2006.
G. Schirner, G. Sachdeva, A. Gerstlauer and R. Dömer, "Embedded Software Development in an System-Level Design Flow: Case Study for an ARM Processor", Proceedings of the International Embedded Systems Symposium, Irvine, CA, 06/2007.
G. Schirner, G. Sachdeva, A. Gerstlauer and R. Dömer, "Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor", TR 06-06, CECS, UC Irvine, 04/2006.
G. Schirner, "System-Level Design of Human-in-the-Loop Cyber-Physical Systems", New England CPS, Natick, MA, 5/2012.
G. Schirner, "The Integration of Algorithm Development Into System Level Design", Mathworks, Natick, MA, 04/09/12, 2012.
G. Schirner, D. Erdogmus, K. Chowdhury and T. Padir, "The Future of Human-in-the-Loop Cyber-Physical Systems", IEEE Computer, vol/lev. 46, pp. 36-45, 2013.
G. Schirner, A. Gerstlauer and R. Dömer, "Abstract, Multifaceted Modeling of Embedded Processors for System Level Design", Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 01/2007.
G. Schirner, "Efficient Embedded System Models Using Result Oriented Modeling", C-LAB, University of Paderborn, Germany, 09/2008.
G. Schirner, "Embedded Systems: System-level Design and Modeling", Analog Devices Inc., Norwood, MA, 06/2011.
G. Schirner, A. Gerstlauer and R. Dömer, "System-level development of embedded software", In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 2010.
G. Schirner and R. Dömer, "Fast and Accurate Transaction Level Models using Result Oriented Modeling", In Proceedings of the International Conference on Computer Aided Design (ICCAD), San Jose, CA, 11/2006.
G. Schirner, M. Götz, A. Rettberg, M. Zanella and F. J. Rammig, Embedded Systems: Design, Analysis and Verification , vol/lev. 403, Springer, 2013.
G. Schirner, "High-Level Specifications to Cope With Design Complexity", Asia and South Pacific Design Automation Conference (ASPDAC), Singapore, 01/2014 .
G. Schirner, "System-Level Design Mitigating Embedded System Design Challenges", Qualcomm , New England, Boxborough, MA, 08/2012.
G. Schirner and R. Dömer, "Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling", ACM Transactions on Embedded Computer Systems, vol/lev. 8, pp. 4:1-4:29, 12/2008.
G. Schirner, "System Level Modeling of an AMBA Bus", Electrical Engineering and Computer Science, vol/lev. MS, Irvine, CA, University of California, Irvine, 2005.
G. Schirner, "Modeling, synthesis, and validation of heterogeneous biomedical embedded systems", High-Level Design, Verification and Test (HLDVT), 2011.
G. Schirner and R. Dömer, Analysis and Optimization of Fast and Accurate SoC Platform Models , San Diego, California, In SIGDA PhD Forum at the Design Automation Conference (DAC), 2007.

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