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G
C. Zhang, H. Tabkhi and G. Schirner, "A GPU-based Algorithm-specific Optimization for High-performance Background Subtraction", International Conference on Parallel Processing, Minneapolis, MN, 2014.
H. Tabkhi, M. Sabbagh and G. Schirner, "Guiding Power/Quality Exploration for Communication-Intense Stream Processing", Great Lakes Symposium on VLSI (GLS-VLSI), Boston (MA), US, 05/2016.
H. Tabkhi, M. Sabbagh and G. Schirner, Guiding Power/Quality Exploration for Communication-Intense Stream Processing , San Francisco, USA, 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 06/2014.
H
A. Momeni, H. Tabkhi, G. Schirner and D. Kaeli, "Hardware thread reordering to boost OpenCL throughput on FPGAs", ICCD, Phoenix (AZ), International Conference on Computer Design, 2016.
S. Abdi, G. Schirner, I. Viskic, H. Cho, Y. Hwang, L. Yu and D. D. Gajski, "Hardware-dependent Software synthesis for many-core embedded systems", In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 01/2009.
G. Schirner, "Hardware/Software Co-Design: System Synthesis Using MATLAB and Simulink", Mathworks, Natick, MA, 04/2012.
G. Schirner, R. Dömer and A. Gerstlauer, "High-Level Development, Modeling and Automatic Generation of Hardware-Dependent Software", Hardware-dependent Software, Springer Netherlands, pp. 203-231, 2009.
G. Schirner, "High-Level Specifications to Cope With Design Complexity", Asia and South Pacific Design Automation Conference (ASPDAC), Singapore, 01/2014 .
H. Tabkhi, "High-Performance Power-Efficient Solutions for embedded vision", Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
H. Tabkhi, High-Performance Power-Efficient Solutions for Embedded Vision Computing , San Francisco, DAC 2015, 2015.
I
J. Zhang, Y. Zhang and M. L. Wang, "The Improvement of Accuracy of Standalone GPS with an Alternative Positioning Algorithm", SPIE Smart Structures and Materials+ Nondestructive Evaluation and Health Monitoring, International Society for Optics and Photonics, 2011.
G. Schirner, "Improving Accuracy of Transaction Level Models in Multi-Processor System-on-Chip Design", Embedded System Design , University of Dortmund, Germany, 12/2007.
N. Teimouri, "Improving Scalability of Chip-MultiProcessors with Many HW ACCelerators", Electrical and Computer Engineering, Boston, Northeastern University, 12/2017.
N. Teimouri, H. Tabkhi and G. Schirner, Improving Scalability of CMPs with Dense ACCs Coverage , Dresden, Germany, DATE, 2016.
A. Agarwal, "Integrating Instruction Set Simulator into a System Level Design Environment", Electrical and Computer Engineering, vol/lev. MSc, Boston, Northeastern , 02/2013.
G. Schirner, "The Integration of Algorithm Development Into System Level Design", Mathworks, Natick, MA, 04/09/12, 2012.
J. Zhang, "Integration of Algorithm-Level Design and System-Level Design: Synthesis, Optimization and Exploration", Electrical and Computer Engineering, Boston, Massachusetts, Northeastern University, 08/2014.
G. Schirner and R. Dömer, "Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling", In Proceedings of Design Automation and Test in Europe (DATE), Munich, Germany, 03, 2008.
J
J. Zhang and G. Schirner, "Joint Algorithm Developing and System-Level Design: Case Study on Video Encoding", International Embedded Systems Symposium (IESS), Paderborn, Germany , 2013.
H. Tabkhi and G. Schirner, "A Joint SW/HW Approach for Reducing Register File Vulnerability", ACM Transactions on Architecture and Code Optimization (ACM TACO), 02/2015, In Press.
L
G. Schirner, T. Harmon and R. Klefstad, "Late Demarshalling: A Technique for Efficient Multi-language Middleware for Embedded Systems", Proceedings of the International symposium on Distributed Objects and Applications (DOA), Larnaca, Cyprus, 10/2004.
M
H. Qiu, "Managing bulk sensor data for heterogeneous distributed systems", Electrical and Computer Engineering, vol/lev. MSc, Boston, Northeastern, 04/2014.

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