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Report
J.. Zhang, H.. Tabkhi and G.. Schirner, Mitigating Application Diversity for Allocating a Unified ACC-Rich Platform , 2019.
X. Han and G. Schirner, "Real-Time MP3 Decoding on FPGA: a Case Study of System Model Features,", Technical Report TR 09-09, CECS, UC Irvine, 07/2009.
D. D. Gajski, S. Abdi, G. Schirner, H. Cho, Y. Hwang, L. Yu, I. Viskic and Q.-V.. Dnag, "Embedded System Environment (Front End) ESE Version 2.0 Evaluation Tutorial", TR 08-15, CECS, UC Irvine, 12/2008.
G. Schirner, D. D. Gajski and S. Abdi, "Requirements and Specification for Multi-Core SW Synthesis", Technical Report TR-08-16, CECS, UC Irvine, 12/2008.
Y. Hwang, G. Schirner and S. Abdi, "Timed RTOS Models in Automatically Generated Cycle-Approximate TLMs", TR-08-12, CECS, UC Irvine, 09/2008.
G. Schirner, G. Sachdeva, A. Gerstlauer and R. Dömer, "Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor", TR 06-06, CECS, UC Irvine, 04/2006.
A. Gerstlauer, G. Schirner, D. Shin and J. Peng, "Necessary and Sufficient Functionality and Parameters for SoC Communication", TR-06-01, 05/2006.
A. Gerstlauer, G. Schirner, D. Shin, J. Peng and R. Dömer, "System-On-Chip Component Models", TR-06-10, CECS, UC Irvine, 05/2006.
G. Schirner, G. Sachdeva, A. Gerstlauer and R. Dömer, "Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor", TR 06-06, CECS, UC Irvine, 04/2006.
A. Gerstlauer, G. Schirner, D. Shin and J. Peng, "Necessary and Sufficient Functionality and Parameters for SoC Communication", TR-06-01, 05/2006.
A. Gerstlauer, G. Schirner, D. Shin, J. Peng and R. Dömer, "System-On-Chip Component Models", TR-06-10, CECS, UC Irvine, 05/2006.
G. Schirner and R. Dömer, "System Level Modeling of an AMBA Bus", TR-05-03, 04/2005.
G. Schirner and R. Dömer, "Using Result Oriented Modeling for Fast yet Accurate TLMs", TR-05-05, CECS, UC Irvine, 05/2005.
P. Chandraiah, G. Schirner, N. Srinivaz and R. Dömer, "System-On Chip Modeling and Design: A Case Study on MP3 Decoder", TR-04-17, CECS, UC Irvine, 06/2004 .
P. Chandraiah, G. Schirner, N. Srinivaz and R. Dömer, "System-On Chip Modeling and Design: A Case Study on MP3 Decoder", TR-04-17, CECS, UC Irvine, 06/2004 .
Thesis
G. Schirner, "Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design", Electrical Engineering and Computer Science, vol/lev. PhD, Irvine, CA, University of California, Irvine, 04/2008.
G. Schirner, "System Level Modeling of an AMBA Bus", Electrical Engineering and Computer Science, vol/lev. MS, Irvine, CA, University of California, Irvine, 2005.
Conference Paper
N. Teimouri, H. Tabkhi and G. Schirner, "Revisiting Accelerator-Based CMPs: Challenges and Solutions", Design Automation Conference (DAC), San Francisco, Design Automation Conference (DAC), 06/2015, In Press.
J. Zhang, H. Tabkhi and G. Schirner, "DS-DSE: Domain-Specific Design Space Exploration for Streaming Applications", Design Automation and Test in Europe (DATE), Dresden, Germany, DATE, 03/2018.
H. Tabkhi, M. Sabbagh and G. Schirner, "Guiding Power/Quality Exploration for Communication-Intense Stream Processing", Great Lakes Symposium on VLSI (GLS-VLSI), Boston (MA), US, 05/2016.
A. Momeni, H. Tabkhi, G. Schirner and D. R. Kaeli, "OpenCL-based optimizations for acceleration of object tracking on FPGAs and GPUs", International Workshop on Architectures and Systems for Real-time Mobile Vision Applications (ASR-MOV), Barcelona, Spain, 03/2016.
S. Feng, M. Tang, F. Quivira, T. Dyson, F. Cuckov and G. Schirner, "An Embedded Device for Brain/Body Signal Acquisition and Processing", International Symposium on Rapid System Prototyping (RSP), Pittsburgh, PA, 2016.
S. Feng, F. Quivira and G. Schirner, Framework for Rapid Development of Embedded Human-in-the-Loop Cyber-Physical Systems , International Conference on BioInformatics and BioEngineering, 2016.
N. Teimouri, H. Tabkhi and G. Schirner, Improving Scalability of CMPs with Dense ACCs Coverage , Dresden, Germany, DATE, 2016.

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