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Filters: First Letter Of Last Name is S and Author is Gunar Schirner  [Clear All Filters]
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G. Schirner, "Efficient Embedded System Models Using Result Oriented Modeling", University of York, York, England, 09/2008.
S. Feng, M. Tang, F. Quivira, T. Dyson, F. Cuckov and G. Schirner, "An Embedded Device for Brain/Body Signal Acquisition and Processing", International Symposium on Rapid System Prototyping (RSP), Pittsburgh, PA, 2016.
G. Schirner, G. Sachdeva, A. Gerstlauer and R. Dömer, "Embedded Software Development in an System-Level Design Flow: Case Study for an ARM Processor", Proceedings of the International Embedded Systems Symposium, Irvine, CA, 06/2007.
D. D. Gajski, S. Abdi, A. Gerstlauer and G. Schirner, Embedded System Design: Modeling, Synthesis and Verification , 2009.
D. D. Gajski, S. Abdi, G. Schirner, H. Cho, Y. Hwang, L. Yu, I. Viskic and Q.-V.. Dnag, "Embedded System Environment (Front End) ESE Version 2.0 Evaluation Tutorial", TR 08-15, CECS, UC Irvine, 12/2008.
G. Schirner, M. Götz, A. Rettberg, M. Zanella and F. J. Rammig, Embedded Systems: Design, Analysis and Verification , vol/lev. 403, Springer, 2013.
G. Schirner, Embedded Systems Laboratory (ESL) Research Overview , Boston, MA, Mathworks Research Faculty Summit, 06/2014.
G. Schirner, "Embedded Systems: System-level Design and Modeling", Analog Devices Inc., Norwood, MA, 06/2011.
A. Momeni, F. Previlion, A. Despopoulos, G. Schirner, J. Kimani and D. Kaeli, "Engaging Sophomores in Embedded Design using Robotics", Workshop on Computer Architecture Education, Portland, OR, 06/2015.
G. Schirner, Exploring SW Performance Using Preemptive RTOS Models , Fairfax, VA, Proceedings of Rapid System Prototyping Symposium, 2010.
A. Momeni, H. Tabkhi, Y. Ukidave, G. Schirner and D. Kaeli, Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA , Boston, MA, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2015.
R. Ubal, D. Schaa, P. Mistry, X. Gong, Y. Ukidave, Z. Chen, G. Schirner and D. R. Kaeli, "Exploring the Heterogeneous Design Space for both Performance and Reliability", Design Automation Conference (DAC), San Francisco, CA, 2014.
G. Schirner, A. Gerstlauer and R. Dömer, "Fast and Accurate Processor Models for efficient MPSoC Design", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol/lev. 15, pp. 10:1-10:26, 02/2010.
G. Schirner and R. Dömer, "Fast and Accurate Transaction Level Models using Result Oriented Modeling", In Proceedings of the International Conference on Computer Aided Design (ICCAD), San Jose, CA, 11/2006.
Y. Ukidave, G. Schirner and D. R. Kaeli, "Fast Fourier Transform (FFT) on GPUs", Numerical Computations with GPUs, Springer International Publishing, pp. 339 - 361, 2014.
R. Bushey, H. Tabkhi and G. Schirner, "Flexible Function-Level Acceleration of Embedded Vision Applications using the Pipelined Vision", Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), 11/2013.
S. Feng, F. Quivira and G. Schirner, Framework for Rapid Development of Embedded Human-in-the-Loop Cyber-Physical Systems , International Conference on BioInformatics and BioEngineering, 2016.
H. Tabkhi, R. Bushey and G. Schirner, "Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications", Springer Journal of Signal Processing and Systems, 2015.
H. Tabkhi, R. Bushey and G. Schirner, "Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs", IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, 2014.
G. Schirner, D. Erdogmus, K. Chowdhury and T. Padir, "The Future of Human-in-the-Loop Cyber-Physical Systems", IEEE Computer, vol/lev. 46, pp. 36-45, 2013.
C. Zhang, H. Tabkhi and G. Schirner, "A GPU-based Algorithm-specific Optimization for High-performance Background Subtraction", International Conference on Parallel Processing, Minneapolis, MN, 2014.
H. Tabkhi, M. Sabbagh and G. Schirner, "Guiding Power/Quality Exploration for Communication-Intense Stream Processing", Great Lakes Symposium on VLSI (GLS-VLSI), Boston (MA), US, 05/2016.
H. Tabkhi, M. Sabbagh and G. Schirner, Guiding Power/Quality Exploration for Communication-Intense Stream Processing , San Francisco, USA, 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 06/2014.
A. Momeni, H. Tabkhi, G. Schirner and D. Kaeli, "Hardware thread reordering to boost OpenCL throughput on FPGAs", ICCD, Phoenix (AZ), International Conference on Computer Design, 2016.
S. Abdi, G. Schirner, I. Viskic, H. Cho, Y. Hwang, L. Yu and D. D. Gajski, "Hardware-dependent Software synthesis for many-core embedded systems", In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 01/2009.


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