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G. Schirner, "High-Level Specifications to Cope With Design Complexity", Asia and South Pacific Design Automation Conference (ASPDAC), Singapore, 01/2014 .
G. Schirner, "System-Level Design of Human-in-the-Loop Cyber-Physical Systems", New England CPS, Natick, MA, 5/2012.
G. Schirner, "Modeling, Synthesis, and Validation of Heterogeneous Biomedical Embedded Systems", High-Level Design, Verification and Test (HLDVT), Napa, CA, 11/2011.
G. Schirner, "System-Level Design Mitigating Embedded System Design Challenges", Worchester Polytechnic Institute, Worchester, MA, 02/03/11, 2011.
G. Schirner, "System-Level Development of Embedded Software", Asia and South Pacific Design Automation Conference (ASPDAC) , Taipei, Taiwan, 01/2010.
G. Schirner, "Efficient Embedded System Models Using Result Oriented Modeling", C-LAB, University of Paderborn, Germany, 09/2008.
G. Schirner, "Efficient Embedded System Models Using Result Oriented Modeling", Offis, University of Oldenburg, Oldenburg, Germany, 09/2008.
G. Schirner, "Efficient Embedded System Models Using Result Oriented Modeling", University of York, York, England, 09/2008.
G. Schirner, "Improving Accuracy of Transaction Level Models in Multi-Processor System-on-Chip Design", Embedded System Design , University of Dortmund, Germany, 12/2007.
G. Schirner, "System-Level Design Mitigating Embedded System Design Challenges", Qualcomm , New England, Boxborough, MA, 08/2012.
G. Schirner, "The Integration of Algorithm Development Into System Level Design", Mathworks, Natick, MA, 04/09/12, 2012.
G. Schirner, "Hardware/Software Co-Design: System Synthesis Using MATLAB and Simulink", Mathworks, Natick, MA, 04/2012.
G. Schirner, "System-Level Design and Estimation", Analog Devices Inc, Norwood, MA, 02/13/12, 2012.
G. Schirner, "Model-based HW/SW Codesign", Mathworks, Natick, MA, 08/2011.
G. Schirner, "Embedded Systems: System-level Design and Modeling", Analog Devices Inc., Norwood, MA, 06/2011.
G. Schirner, "CORBA in Telecommunication Products", half-day tutorial with Antonio Fontan, Alcatel USA (aud.: 45 system designers and SW engineers), Petaluma, CA, 04/2002.
G. Schirner, "Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design", Electrical Engineering and Computer Science, vol/lev. PhD, Irvine, CA, University of California, Irvine, 04/2008.
G. Schirner, "System Level Modeling of an AMBA Bus", Electrical Engineering and Computer Science, vol/lev. MS, Irvine, CA, University of California, Irvine, 2005.
G. Schirner, Embedded Systems Laboratory (ESL) Research Overview , Boston, MA, Mathworks Research Faculty Summit, 06/2014.

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