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Export 6 results:
Author Keyword Title Type [ Year
] Filters: Author is Yonghyun Hwang [Clear All Filters]
"Automatic TLM Generation for Early Validation of Multicore Systems",
IEEE Design and Test of Computers, vol/lev. 28, pp. 10-19, 2011.
"Accurate Timed RTOS Model for Transaction Level Modeling",
Proceedings of Design Automation and Test in Europe (DATE), Dresden, Germany, 2010.
"Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support",
Analysis, Architectures and Modelling of Embedded Systems, Springer Berlin Heidelberg, 2009.
"Hardware-dependent Software synthesis for many-core embedded systems",
In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 01/2009.
"Embedded System Environment (Front End) ESE Version 2.0 Evaluation Tutorial",
TR 08-15, CECS, UC Irvine, 12/2008.
"Timed RTOS Models in Automatically Generated Cycle-Approximate TLMs",
TR-08-12, CECS, UC Irvine, 09/2008.
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