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2008
G. Schirner and R. Dömer, "Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling", ACM Transactions on Embedded Computer Systems, vol/lev. 8, pp. 4:1-4:29, 12/2008.
G. Schirner, D. D. Gajski and S. Abdi, "Requirements and Specification for Multi-Core SW Synthesis", Technical Report TR-08-16, CECS, UC Irvine, 12/2008.
Y. Hwang, G. Schirner and S. Abdi, "Timed RTOS Models in Automatically Generated Cycle-Approximate TLMs", TR-08-12, CECS, UC Irvine, 09/2008.
2009
Y. Hwang, G. Schirner and S. Abdi, "Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support", Analysis, Architectures and Modelling of Embedded Systems, Springer Berlin Heidelberg, 2009.
D. D. Gajski, S. Abdi, A. Gerstlauer and G. Schirner, Embedded System Design: Modeling, Synthesis and Verification , 2009.
S. Abdi, G. Schirner, I. Viskic, H. Cho, Y. Hwang, L. Yu and D. D. Gajski, "Hardware-dependent Software synthesis for many-core embedded systems", In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 01/2009.
G. Schirner, R. Dömer and A. Gerstlauer, "High-Level Development, Modeling and Automatic Generation of Hardware-Dependent Software", Hardware-dependent Software, Springer Netherlands, pp. 203-231, 2009.
X. Han and G. Schirner, "Real-Time MP3 Decoding on FPGA: a Case Study of System Model Features,", Technical Report TR 09-09, CECS, UC Irvine, 07/2009.
2010
Y. Hwang, G. Schirner, S. Abdi and D. D. Gajski, "Accurate Timed RTOS Model for Transaction Level Modeling", Proceedings of Design Automation and Test in Europe (DATE), Dresden, Germany, 2010.
G. Schirner, Exploring SW Performance Using Preemptive RTOS Models , Fairfax, VA, Proceedings of Rapid System Prototyping Symposium, 2010.
G. Schirner, A. Gerstlauer and R. Dömer, "Fast and Accurate Processor Models for efficient MPSoC Design", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol/lev. 15, pp. 10:1-10:26, 02/2010.
A. Gerstlauer and G. Schirner, "Platform Modeling for Exploration and Synthesis", In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Piscataway, NJ, USA, IEEE Press, 2010.
G. Schirner, A. Gerstlauer and R. Dömer, "System-level development of embedded software", In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 2010.
G. Schirner, "System-Level Development of Embedded Software", Asia and South Pacific Design Automation Conference (ASPDAC) , Taipei, Taiwan, 01/2010.
2011
S. Abdi, Y. Hwang, L. Yu, G. Schirner and D. D. Gajski, "Automatic TLM Generation for Early Validation of Multicore Systems", IEEE Design and Test of Computers, vol/lev. 28, pp. 10-19, 2011.
G. Schirner, "Embedded Systems: System-level Design and Modeling", Analog Devices Inc., Norwood, MA, 06/2011.
G. Schirner, "Model-based HW/SW Codesign", Mathworks, Natick, MA, 08/2011.
G. Schirner, "Modeling, synthesis, and validation of heterogeneous biomedical embedded systems", High-Level Design, Verification and Test (HLDVT), 2011.
G. Schirner, "Modeling, Synthesis, and Validation of Heterogeneous Biomedical Embedded Systems", High-Level Design, Verification and Test (HLDVT), Napa, CA, 11/2011.
G. Schirner, "System-Level Design Mitigating Embedded System Design Challenges", Worchester Polytechnic Institute, Worchester, MA, 02/03/11, 2011.
2012
H. Tabkhi and G. Schirner, "AFReP: Application-guided Function-level Registerfile power-gating for embedded processors", International Conference on Computer-Aided Design (ICCAD), 2012.
H. Tabkhi and G. Schirner, "Application-specific power-efficient approach for reducing register file vulnerability", Design Automation and Test In Europe (DATE), 2012.
H. Tabkhi and G. Schirner, "ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2012.
G. Schirner, "Hardware/Software Co-Design: System Synthesis Using MATLAB and Simulink", Mathworks, Natick, MA, 04/2012.
G. Schirner, "The Integration of Algorithm Development Into System Level Design", Mathworks, Natick, MA, 04/09/12, 2012.

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