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Export 107 results:
Author Keyword [ Title
] Type Year Filters: Author is Gunar Schirner [Clear All Filters]
"Rapid, High-Level Performance Estimation for DSE using Calibrated Weight Tables",
IESS, Foz do Iguacu, Brazil, 2015.
"Rapid Heterogeneous Prototyping From Simulink",
International Symposium on Quality Electronic Design (ISQED), 03/2015.
Rapid Embedded Realization of Brain Computer Interfacing Applications
, INV-14090 , 04/2014.
"Quantitative Analysis of Transaction Level Models for the AMBA Bus",
Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, 03/2006.
"Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling",
ACM Transactions on Embedded Computer Systems, vol/lev. 8, pp. 4:1-4:29, 12/2008.
"Quantifying the energy efficiency of FFT on heterogeneous platforms",
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013.
"A Power-efficient Real-time Solution for Adaptive Vision",
IET Computers & Digital Techniques, 2014.
A Power-efficient FPGA-based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution
, FCCM, 2014.
"Platform Modeling for Exploration and Synthesis",
In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Piscataway, NJ, USA, IEEE Press, 2010.
"Optimization of Energy Efficient Relay Position for Galvanic Coupled Intra-body Communication",
IEEE WCNC, 2015.
"OpenCL-based optimizations for acceleration of object tracking on FPGAs and GPUs",
International Workshop on Architectures and Systems for Real-time Mobile Vision Applications (ASR-MOV), Barcelona, Spain, 03/2016.
"A Novel Quantitative ESL Based SOC Architecture Exploration Methodology",
Analog Devices General Technical Conference (ADI GTC), April, 2013.
"The Next Generation Transportation Infrastructure Performance Inspection: A CPS Approach",
NSF Young Professionals Workshop on Cyber Physical Systems, Washington D.C, 02/2014.
"Necessary and Sufficient Functionality and Parameters for SoC Communication",
TR-06-01, 05/2006.
"Multi-path Model and Sensitivity Analysis for Galvanic Coupled Intra-body Communication through Layered Tissue",
IEEE Transactions on Biomedical Circuits and Systems, 05/2015, In Press.
"Multi-path 2-Port Channel Characterization for Galvanic Coupled Intra-body Communication",
BodyNets, London UK, International Conference on Body Area Networks, 09/2014.
"Modeling, Synthesis, and Validation of Heterogeneous Biomedical Embedded Systems",
High-Level Design, Verification and Test (HLDVT), Napa, CA, 11/2011.
"Modeling, synthesis, and validation of heterogeneous biomedical embedded systems",
High-Level Design, Verification and Test (HLDVT), 2011.
"Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor",
TR 06-06, CECS, UC Irvine, 04/2006.
"Modeling and Analysis of SLDL-captured NoC Abstractions",
IESS, Foz do Iguacu, Brazil, 2015.
"Model-based HW/SW Codesign",
Mathworks, Natick, MA, 08/2011.
"A Mobile Platform Approach to integrating active learing accross the EE/CE/ICT Engineering Curriculum",
Proceedings of the European Workshop on Microelectronics Education, Grenoble, France, 05/2012.
"Late Demarshalling: A Technique for Efficient Multi-language Middleware for Embedded Systems",
Proceedings of the International symposium on Distributed Objects and Applications (DOA), Larnaca, Cyprus, 10/2004.
"A Joint SW/HW Approach for Reducing Register File Vulnerability",
ACM Transactions on Architecture and Code Optimization (ACM TACO), 02/2015, In Press.
"Joint Algorithm Developing and System-Level Design: Case Study on Video Encoding",
International Embedded Systems Symposium (IESS), Paderborn, Germany , 2013.
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