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Filters: Type is Conference Paper and Author is Gunar Schirner  [Clear All Filters]
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H. Tabkhi, R. Bushey and G. Schirner, "Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs", IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, 2014.
S. Feng, F. Quivira and G. Schirner, Framework for Rapid Development of Embedded Human-in-the-Loop Cyber-Physical Systems , International Conference on BioInformatics and BioEngineering, 2016.
R. Bushey, H. Tabkhi and G. Schirner, "Flexible Function-Level Acceleration of Embedded Vision Applications using the Pipelined Vision", Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), 11/2013.
G. Schirner and R. Dömer, "Fast and Accurate Transaction Level Models using Result Oriented Modeling", In Proceedings of the International Conference on Computer Aided Design (ICCAD), San Jose, CA, 11/2006.
E
R. Ubal, D. Schaa, P. Mistry, X. Gong, Y. Ukidave, Z. Chen, G. Schirner and D. R. Kaeli, "Exploring the Heterogeneous Design Space for both Performance and Reliability", Design Automation Conference (DAC), San Francisco, CA, 2014.
A. Momeni, H. Tabkhi, Y. Ukidave, G. Schirner and D. Kaeli, Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA , Boston, MA, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2015.
G. Schirner, Exploring SW Performance Using Preemptive RTOS Models , Fairfax, VA, Proceedings of Rapid System Prototyping Symposium, 2010.
A. Momeni, F. Previlion, A. Despopoulos, G. Schirner, J. Kimani and D. Kaeli, "Engaging Sophomores in Embedded Design using Robotics", Workshop on Computer Architecture Education, Portland, OR, 06/2015.
G. Schirner, G. Sachdeva, A. Gerstlauer and R. Dömer, "Embedded Software Development in an System-Level Design Flow: Case Study for an ARM Processor", Proceedings of the International Embedded Systems Symposium, Irvine, CA, 06/2007.
S. Feng, M. Tang, F. Quivira, T. Dyson, F. Cuckov and G. Schirner, "An Embedded Device for Brain/Body Signal Acquisition and Processing", International Symposium on Rapid System Prototyping (RSP), Pittsburgh, PA, 2016.
H. Tabkhi, M. Sabbagh and G. Schirner, "An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction", IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAPs), Toronto, Canada, 2015.
D
J. Zhang, H. Tabkhi and G. Schirner, "DS-DSE: Domain-Specific Design Space Exploration for Streaming Applications", Design Automation and Test in Europe (DATE), Dresden, Germany, DATE, 03/2018.
A
J. Zhang and G. Schirner, "Automatic Specification Granularity Tuning for Design Space Exploration", Proceedings of the ACM/IEEE Conference on Design, Automation & Test in Europe (DATE), Dresden, Germany, 03/2014.
G. Schirner, A. Gerstlauer and R. Dömer, "Automatic Generation of Hardware dependent Software for MPSoCs from Abstract System Specifications", Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, 11/2008.
Y. Hwang, G. Schirner and S. Abdi, "Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support", Analysis, Architectures and Modelling of Embedded Systems, Springer Berlin Heidelberg, 2009.
H. Tabkhi and G. Schirner, "ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2012.
H. Tabkhi and G. Schirner, "Application-specific power-efficient approach for reducing register file vulnerability", Design Automation and Test In Europe (DATE), 2012.
G. Schirner and R. Dömer, Analysis and Optimization of Fast and Accurate SoC Platform Models , San Diego, California, In SIGDA PhD Forum at the Design Automation Conference (DAC), 2007.
H. Tabkhi, R. Bushey and G. Schirner, "Algorithm and Architecture Co-Design of Mixture of Gaussian (MoG) Background Subtraction for Embedded Vision Processor", Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), 11/2013.
H. Tabkhi and G. Schirner, "AFReP: Application-guided Function-level Registerfile power-gating for embedded processors", International Conference on Computer-Aided Design (ICCAD), 2012.
G. Schirner and R. Dömer, "Accurate yet Fast Modeling of Real-Time Communication", Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES ISSS), Seoul, Korea, 10/2006.
Y. Hwang, G. Schirner, S. Abdi and D. D. Gajski, "Accurate Timed RTOS Model for Transaction Level Modeling", Proceedings of Design Automation and Test in Europe (DATE), Dresden, Germany, 2010.
G. Schirner, A. Gerstlauer and R. Dömer, "Abstract, Multifaceted Modeling of Embedded Processors for System Level Design", Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 01/2007.

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