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Report
X. Han and G. Schirner, "Real-Time MP3 Decoding on FPGA: a Case Study of System Model Features,", Technical Report TR 09-09, CECS, UC Irvine, 07/2009.
G. Schirner, D. D. Gajski and S. Abdi, "Requirements and Specification for Multi-Core SW Synthesis", Technical Report TR-08-16, CECS, UC Irvine, 12/2008.
D. D. Gajski, S. Abdi, G. Schirner, H. Cho, Y. Hwang, L. Yu, I. Viskic and Q.-V.. Dnag, "Embedded System Environment (Front End) ESE Version 2.0 Evaluation Tutorial", TR 08-15, CECS, UC Irvine, 12/2008.
Y. Hwang, G. Schirner and S. Abdi, "Timed RTOS Models in Automatically Generated Cycle-Approximate TLMs", TR-08-12, CECS, UC Irvine, 09/2008.
A. Gerstlauer, G. Schirner, D. Shin and J. Peng, "Necessary and Sufficient Functionality and Parameters for SoC Communication", TR-06-01, 05/2006.
G. Schirner, G. Sachdeva, A. Gerstlauer and R. Dömer, "Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor", TR 06-06, CECS, UC Irvine, 04/2006.
A. Gerstlauer, G. Schirner, D. Shin, J. Peng and R. Dömer, "System-On-Chip Component Models", TR-06-10, CECS, UC Irvine, 05/2006.
G. Schirner and R. Dömer, "Using Result Oriented Modeling for Fast yet Accurate TLMs", TR-05-05, CECS, UC Irvine, 05/2005.
G. Schirner and R. Dömer, "System Level Modeling of an AMBA Bus", TR-05-03, 04/2005.
P. Chandraiah, G. Schirner, N. Srinivaz and R. Dömer, "System-On Chip Modeling and Design: A Case Study on MP3 Decoder", TR-04-17, CECS, UC Irvine, 06/2004 .

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