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Conference Paper
S. Feng, M. Tang, F. Quivira, T. Dyson, F. Cuckov and G. Schirner, "An Embedded Device for Brain/Body Signal Acquisition and Processing", International Symposium on Rapid System Prototyping (RSP), Pittsburgh, PA, 2016.
H. Tabkhi, M. Sabbagh and G. Schirner, "An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction", IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAPs), Toronto, Canada, 2015.
A. Momeni, F. Previlion, A. Despopoulos, G. Schirner, J. Kimani and D. Kaeli, "Engaging Sophomores in Embedded Design using Robotics", Workshop on Computer Architecture Education, Portland, OR, 06/2015.
A. Momeni, H. Tabkhi, Y. Ukidave, G. Schirner and D. Kaeli, Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA , Boston, MA, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2015.
R. Ubal, D. Schaa, P. Mistry, X. Gong, Y. Ukidave, Z. Chen, G. Schirner and D. R. Kaeli, "Exploring the Heterogeneous Design Space for both Performance and Reliability", Design Automation Conference (DAC), San Francisco, CA, 2014.
N. Teimouri, M. Modarressi, A. Tavakkol and H. Sarbazi-Azad, "Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths", Architecture of Computing Systems - {ARCS} 2011 - 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings, 2011.
G. Schirner, Exploring SW Performance Using Preemptive RTOS Models , Fairfax, VA, Proceedings of Rapid System Prototyping Symposium, 2010.
A. Patooghy, H. Tabkhi and M. S.G, "An Efficient Method to Reliable Data Transmission in Network-on-Chips", 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), 09/2010.
G. Schirner, G. Sachdeva, A. Gerstlauer and R. Dömer, "Embedded Software Development in an System-Level Design Flow: Case Study for an ARM Processor", Proceedings of the International Embedded Systems Symposium, Irvine, CA, 06/2007.
Thesis
R. Kangralkar, "Enhancing a System-Level Design Flow by RTOS Integration", Electrical and Computer Engineering, vol/lev. Master of Science, Boston, Massachusetts, Northeastern University, pp. 93, 07/2012.
Poster
G. Schirner, Embedded Systems Laboratory (ESL) Research Overview , Boston, MA, Mathworks Research Faculty Summit, 06/2014.

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