You are here

ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors

In this paper, we introduce an Application-guided Reliability-enhanced Register file Architecture (ARRA) to improve the reliability of RF in embedded processors. ARRA proposes a RF micro-architecture which is guided by binary instrumentation for run-time register mirroring. Our experimental results on an ARRA-enhanced Blackfin processor present that on average the power overhead of ARRA is 70% less than that of a partially-ECC-protected RF, while ARRA reduces RF Vulnerability Factor from 35% to 6.9%, and can correct up to three bit-flips errors.

Appeared in:
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Related Research:  Cross Layer Optimizations for Processors with Large Register Files

Theme by Danetsoft and Danang Probo Sayekti inspired by Maksimer