The System-On-Chip (SoC) design faces a gap between the production capabilities and time to market pressures. The design space, to be explored during the SoC design, grows with the
improvements in the production capabilities and it takes an increasing amount of time to design a system that utilizes those capabilities. On the other hand shorter product life cycles are forcing an aggressive reduction of the time-to-market. Addressing this gap has been the aim of recent research work. As one approach abstract models have been introduced and a design flow was devised that guides the designer in the process from a most abstract model down to a synthesizable model. Throughout the design process computation and communication concerns are handled individually. The communication is mostly abstracted away from the designer, which allows the design focus to rest on the application specific computation. This separation requires the provider of an SoC design tool to supply fast and accurate communication models.
Fast simulation capabilities are required for coping with the immense design space that is to be explored; these are especially needed during early stages of the design. This need has pushed the development of transaction level models, which are abstract models that execute dramatically faster than synthesizable models. The pressure for fast executing models extends especially to
the frequently used and reused communication libraries. This thesis describes the system level modeling of the Advanced High-performance Bus (AHB) part of the Advanced Microprocessor
Bus Architecture (AMBA). Throughout this work the design of three bus models, at different levels of abstraction, is described; their simulation speed and accuracy is evaluated. As a result guidelines for the developer are derived that support selecting the most appropriate model for a given stage in the design process.
Electrical Engineering and Computer ScienceUniversity of California, Irvine