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Revisiting Accelerator-Based CMPs: Challenges and Solutions

Heterogeneous CMPs combining processor cores with specialized HW accelerators are a main approach for high-performance low-power computing. While it is promising for few accelerators, the scalability is a major challenge with increasing number of accelerators. Resources including memory, communication fabric and processor turn into bottlenecks and result in accelerator under-utilization and cripple the performance.

This paper analyzes the scalability of heterogeneous CMPs with many accelerators and identifies bottlenecks and their impacts on system performance. It introduces an analytical method for scalability/bottleneck analysis which is backed up by a simulation-based performance analysis (using automatically generated virtual platforms). This paper proposes a novel architecture template: Transparent Self-Synchronized (TSS) accelerators for efficient/scalable realization of streaming applications. TSS achieves the efficiency/scalability through configurable point-to-point connections and self-synchronization between HW accelerators and efficient management of accelerator's memory.

This article demonstrates the TSS benefits using both analytical and simulation methods. TSS significantly reduces the pressure on the communication fabric, processor load, and memory requirements to improve scalability. Even with increasing number of accelerators, TSS can achieve more than 85\% accelerator utilization depending on how large memory is available. While in ACC-based CMP accelerator utilization drops fast, less than 40\% with 6 accelerators or even worse with more accelerators. The scalability benefits of TSS are more pronounced as the number of hardware accelerators increases.

Appeared in:
Design Automation Conference (DAC)Design Automation Conference (DAC)
In Press
Presentation Place:
San Francisco
Related Research:  Novel Architecture for Streaming Applications



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