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Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths

Topology is an important network attribute that greatly affects the power, performance, cost, and design time/effort of NoCs. In this paper, we propose a novel NoC architecture that can exploit the benefits of both application-specific and regular NoC topologies. To this end, a subset of NoC links bypass the router pipeline stages and directly connect remotely located nodes. This results in an NoC which holds both fixed connections between adjacent nodes and long connections virtually connecting non-adjacent nodes. These shortcut paths are constructed at run-time by employing a simple and fast mechanism composed of two processes: on-chip traffic monitoring and path reconfiguration. The former keeps the track of the changes in the on-chip traffic pattern and detects high-volume communication flows. The latter then adapts the shortcut paths to the current on-chip traffic pattern by constructing shortcut paths between the source and destination nodes of the high-volume communication flows. Supporting the shortcut paths imposes a trivial overhead on the area of a conventional packet-switched router. Experimental results reveal the effectiveness of the proposed technique in reducing the energy consumption and improving the performance of NoCs.

Appeared in:
Architecture of Computing Systems - {ARCS} 2011 - 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings

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