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Application-Guided Power Gating Reducing Register File Static Power

Power and energy efficiency are on the top priority list in embedded computing. Embedded processors taped out in deep sub-micron technology have a high contribution of static power to overall power consumption. At the same time, current embedded processors often include a large Register File (RF) to
increase performance. However, a larger RF aggravates the static power issues associated with technology shrinking. Therefore, approaches to improve static power consumption of large RFs are in high demand. In this paper, we introduce AFReP: an Application-guided Function-level Registerfile Power-gating approach to efficiently manage and reduce RFs static power consumption. AFReP is an interplay of automatic binary analysis and instrumentation at function-level granularity supported by ISA and microarchitecture extensions. AFReP enables runtime power-gating of registers during un-utilized periods, while applications can fully benefit from a large RF during utilized periods. To demonstrate AFReP’s potential for reducing static power consumption, we have enhanced a Blackfin processor with the AFReP technology. Using AFReP, the RF static power is reduced on average by 64% and 39% for control and DSP applications, respectively. At the
same time, AFReP only induces a very minimal overhead of 0.4% and 0.6%.

Appeared in:
IEEE Transactions on Very Large Scale Integration (TVLSI)

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