Integrating Instruction Set Simulator into a System Level Design Environment
Design of Embedded System, which today comprises of both Hardware and Software (HW/SW) has become complex with the advancement of technology and with the ever increasing demand for complex and low cost features. Systems developed today should arrive must arrive at market quickly and at the same time meet the constraints of power, memory and cost. As one solution, designers are moving to higher level of abstraction or System Level design
which covers both Hardware (HW) and Software (SW). This is realized through a model based design methodology which utilizes virtual environment for early validation of the specification and at the same time also provides for verification of functionality of the system. It also augments the design process by providing a pre-silicon prototype of the final physical system for software development and allows for and helps in performance tuning of these complex systems. Furthermore, virtual platforms can also serve as inputs to Register Transfer Level (RTL) and software component synthesis for the system.
Modern Embedded Systems are heterogeneous as they have both a programmable processor core and dedicated hardware units that is the virtual platform which simulates the system. Instruction Set Simulator (ISS) provide a simulation environment for programmable processors and are utilized in a virtual environment to validate software running on programmable processor. Today there are many stand-alone ISS which are available in the open source community, however they are not integrated with a system design tool suite making it impossible to utilize them to validate SW. Manual effort to individually add them to a system-level design tool suite requires work for each addition and is prone to error.
In this thesis we focus on providing a generalized guidelines for integrating ISS´s to a system-level design tool. The guidelines are developed in order to simplify the process of adding an ISS to a system level design tool. The developed guidelines takes into account the requirements to model communication between processor and other computing components in an System on Chip (SoC), and also provide to interrupt based synchronization capability between components. It also takes into account the requirements to reduce simulation time which is a major bottleneck and which limits the use of system simulation. The guidelines developed also take into account different types of ISS, one which simulate only the processor core and the other ones which simulate both the core
and peripheral of the processor together. We validate the generalized guidelines by integrating a Blackfin family processor ISS available under GNU tool chain with a system level design tool System on Chip Environment (SCE), which support modeling, synthesis and validation of Heterogeneous Embedded Systems.
Electrical and Computer EngineeringNortheastern