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Enhancing a System-Level Design Flow by RTOS Integration

The complexity of designing modern embedded system is increasing at exponential rate. Electronic System Level (ESL) design methodology and System Level Design Languages (SLDL) have been introduced to address the complexity in design. ESL focuses on higher design abstraction level, and SLDL aid in capturing the specification.
In modern embedded systems, the design cost of software content is high compared to hardware. Very often embedded system software consists of a Real Time Operating System (RTOS) with multi-threaded applications executing on heterogeneous multi-processor systems. Dynamic scheduling behavior, task distribution, priority assignment and latencies of an application executing on an RTOS are important non-functional considerations during design space exploration. ESL aids in generation and synthesis of hardware and software models. The synthesized hardware models offer functional simulation of physical hardware. The functional simulation model of physical hardware forms virtual platform. The virtual platform can be used for the purpose of testing the generated software. Execution of software on virtual platform aids for better profiling, analyzing and debugging of systems facilitate design space exploration. The work in this thesis introduces support for a commonly used RTOS, Real-Time Executive for Multiprocessor Systems (RTEMS) for both ARM and Blackfin processor into an ESL flow tool System-on-Chip Environment (SCE). We use the Portable Operating System Interface (POSIX) standard for interfacing the generated software to RTEMS. Using POSIX standard allows future integration of POSIX compliant operating systems into ESL. To demonstrate the flexibility offered by our approach, we synthesize a JPEG decoder along with RTEMS on ARM and Blackfin processor. The synthesized JPEG encoder is used as load while measuring the cumulative probability of response time for each RTOS. The response time provides system designers with accurate system latencies of the RTOS. In this thesis we explore the design space by synthesizing a JPEG decoder with μC/OS-II, RTEMS on ARM and ADSP-BF527 processor. The experimental results show that the maximum response latency of μC/OS-II is about 41% lower than RTEMS on ARM processors. Thus using our work the system designer can automatically synthesize an RTOS and explore the RTOS characteristics for an embedded application.

Appeared in:
Electrical and Computer EngineeringNortheastern University
Presentation Place:
Boston, Massachusetts

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