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Modeling and Analysis of SLDL-captured NoC Abstractions

With increasing number of IP cores, parallel communication architectures including NoCs have emerged as dominating solutions for many-core systems. To efficiently impalement NoC, early modeling and analysis of crucial NoC run-time metrics such as throughput, latency and saturation time is required. The granularity and accuracy of these collected metrics have direct correlation with the abstraction level of modeled NoC; smaller granularity leads to higher accuracy at the cost of slower analysis. Conversely, fast analysis of NoC loses accuracy as there is a trade-off between analysis speed and accuracy. The first contribution of this paper is identifying possible levels of abstraction for NoC models and correlate expressed features of them with the accuracy and speed trade-off.

The second contribution of this paper is proposing 2 models of NoC with different levels of abstraction; pin-accurate (with lower abstraction level) and transactionaccurate (with higher abstraction level). The proposed models are captured in SpecC -SLDL- with the same router architecture model but different approaches for updating the system status which affects on the accuracy. The former updates the system status after any events happening during data unit transfer, while the latter updates the system status at the end of data unit transfer. Our evaluation results show moving to higher abstraction (from pin-accurate level to transaction-accurate level) can gain us 10 times speedup at the cost of only 10-20 % accuracy loss. The main goal of our analysis approach and results is guiding system architects in exploring NoC architectural alternatives and identifying suitable abstract models based on desired accuracy and analysis speed.

Appeared in:
Presentation Place:
Foz do Iguacu, Brazil
Related Research:  Network on Chip

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