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Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs

This paper introduces Function-Level Processors (FLPs) to fill the flexibility/efficiency gap between Instruction- Level Processors (ILPs) and Hardware Accelerators (HWACCs). Compared to an ILP, an FLP has a coarser programmability at function-level constructed out of configurable Function Blocks (FBs) implementing market-oriented functions. FBs are connected via a MUX-based programmable interconnect, tuned for envisioned application flows, for realizing flexible macro pipelines.
We demonstrate FLP benefits with an industry example of the Pipeline-Vision Processor (PVP). Mapping six embedded vision applications, the PVP offers up to 22.4 GOPs/s with average power of 120 mW; consuming 17x and 6x less power than compared ILP and ILP+HWACCs approaches.

Appeared in:
IEEE Embedded Systems Letters (accepted 5/20/14)
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