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Towards Closing the Specification Gap by Integrating Algorithm-Level and System-Level Design

Modern Multiprocessor System-on-Chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality

and architecture. Algorithm-Level Design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, SystemLevel Design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from

specifications captured in a System-Level Design Language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle.

This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm

according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture codesign flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and

architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and errorprone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 hours of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models.

Appeared in:
Springer Design Automation for Embedded Systems (DAEM)
Related Research:  Algo2Spec: Integrating Algorithm Development and System-level Design

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