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An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction

Embedded Vision is a rapidly growing market with a host of challenging algorithms. Among vision algorithms, Mixture of Gaussian (MoG) background subtraction is a frequently used kernel involving massive computation. Providing MoG’s required high computation performance while observing the power limitation of embedded systems poses tremendous challenges for an embedded deployment of MoG.
This paper proposes a customized architecture solution for power-efficient realization of MoG background subtraction operating at Full-HD frame resolution. Our design process benefits from system-level design principles. An SLDL-captured specification (result of high-level explorations) serves as a specification for architecture realization and hand-crafted RTL design. To optimize the architecture, this paper employs a set of optimization techniques including parallelism extraction, algorithm tuning, operation width sizing and deep pipelining. The final MoG implementation consists of 77 pipeline stages operating at 148.5 MHz implemented on a Zynq-7000 SoC. Furthermore, our background subtraction solution is flexible allowing end users to adjust algorithm parameters according to scene complexity. Our results demonstrate a very high efficiency for both indoor and outdoor scenes with a power consumption of less than 500 mW with more than 600x speedup over software implementation over ARM Cortex A9 core.
Appeared in:
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAPs)
Presentation Place:
Toronto, Canada
Related Research:  Novel Architecture for Streaming Applications

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