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Embedded Systems: Design, Analysis and Verification
, vol/lev. 403, Springer, 2013.
"Fast Fourier Transform (FFT) on GPUs",
Numerical Computations with GPUs, Springer International Publishing, pp. 339 - 361, 2014.
"System Level Design of a Roaming Multi-Modal Multi-Sensor System",
Sensor Technologies for Civil Infrastructures: Performance Assessment & Health Monitoring, Woodhead Publishing, 2014.
"High-Level Development, Modeling and Automatic Generation of Hardware-Dependent Software",
Hardware-dependent Software, Springer Netherlands, pp. 203-231, 2009.
"Multi-path Model and Sensitivity Analysis for Galvanic Coupled Intra-body Communication through Layered Tissue",
IEEE Transactions on Biomedical Circuits and Systems, 05/2015, In Press.
"A Joint SW/HW Approach for Reducing Register File Vulnerability",
ACM Transactions on Architecture and Code Optimization (ACM TACO), 02/2015, In Press.
"Alleviating Scalability Limitation of Accelerator-based Platforms",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2018.
"Towards Closing the Specification Gap by Integrating Algorithm-Level and System-Level Design",
Springer Design Automation for Embedded Systems (DAEM), 2015.
"Studying Inter-Warp Divergence Aware Execution on GPUs",
Computer Architecture Letters, 2015.
"Conceptual Abstraction Levels (CALs) for Managing Design Complexity of Market-Oriented MPSoCs",
Elsevier Journal of Microprocessors and Microsystems, 2015.
"Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications",
Springer Journal of Signal Processing and Systems, 2015.
"Simultaneous hardware and time redundancy with online task scheduling for low energy highly reliable standby-sparing system",
{ACM} Trans. Embedded Comput. Syst., vol/lev. 13, pp. 86:1–86:31, 2014.
"Analyzing Power Efficiency of Optimization Techniques and Algorithm Design Methods for Applications on Heterogeneous Platforms",
International Journal of High Performance Computing Applications (IJHPCA), 2014.
"Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs",
IEEE Embedded Systems Letters (accepted 5/20/14), 05/2014.
"Application-Guided Power Gating Reducing Register File Static Power",
IEEE Transactions on Very Large Scale Integration (TVLSI), 2014.
"A Power-efficient Real-time Solution for Adaptive Vision",
IET Computers & Digital Techniques, 2014.
"The Future of Human-in-the-Loop Cyber-Physical Systems",
IEEE Computer, vol/lev. 46, pp. 36-45, 2013.
"Automatic TLM Generation for Early Validation of Multicore Systems",
IEEE Design and Test of Computers, vol/lev. 28, pp. 10-19, 2011.
"A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips",
Microprocessors and Microsystems - Embedded Hardware Design, vol/lev. 35, pp. 766-778, 2011.
"Fast and Accurate Processor Models for efficient MPSoC Design",
ACM Transactions on Design Automation of Electronic Systems (TODAES), vol/lev. 15, pp. 10:1-10:26, 02/2010.
"Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling",
ACM Transactions on Embedded Computer Systems, vol/lev. 8, pp. 4:1-4:29, 12/2008.
"Result Oriented Modeling a Novel Technique for Fast and Accurate TLM",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol/lev. 26, pp. 1688-1699, 09/2007.
"Revisiting Accelerator-Based CMPs: Challenges and Solutions",
Design Automation Conference (DAC), San Francisco, Design Automation Conference (DAC), 06/2015, In Press.
"DS-DSE: Domain-Specific Design Space Exploration for Streaming Applications",
Design Automation and Test in Europe (DATE), Dresden, Germany, DATE, 03/2018.
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