This week, Professor Schirner attends ASAP 2014 to present his recently accepted work on the Function-Level Processor (FLP) general architecture, its programming and an efficiency evaluation[1]. The relatred research project on hwich this paper is generated, can be found here.

References

1. H. Tabkhi, R. Bushey and G. Schirner, Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, 2014
   
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