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Network on Chip

Leader: 
Nasibeh Teimouri
Member:  Kasra Moazzami, Ran Hao
Year:  2013
The existent trade-off between simulation speed and simulation accuracy, has motivated us to define this project. In this project, we propose some abstract models of Network-on Chip (NoC) in a hierarchy. This abstraction hierarchy, from top to down, includes observing NoC as a black box to taking all the wires connection and transactions into account, provides the designer with an appropriate model with its specific level of accuracy and speed. 
At the second step, two abstract models in hierarchy are implemented with SpecC. These two models are selected from the middle of hierarchy, one is accurate as cycle accurate simulator and the other is fast at the cost of accuracy. 
As the final step, using the implemented models, we investigate the factors have effects on accuracy in abstraction. 
  

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