Modern embedded processors increasingly utilize larger register files. While large register files improve performance, reducing accesses to the memory hierarchy, they also have a considerable contribution in processor static power and a significant contribution to embedded processors reliability. At the same time, not all registers are used in all applications. However, the processor core itself is not aware of register utilization and in particular cannot predict if a register will be read in the future (ie. is active), or will be written to in the future (ie. is passive). This line of research introduces cross layer optimizations that utilize application binary analysis, instrumentation, and execution on an improved architecture. This offers opportunity to reduce static power consumption, and improving reliability of register files.