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Embedded Software Development in a System Level Design Context

Year:  2006

System level design is one approach to tackle the complexity of designing a modern System-on-Chip. One major aspect is the capability of developing the system model without a special attention to the later occurring hardware software split. Both hardware and software can be developed seamlessly at the same time. It therefore allows a better integration between those traditionally separated development flows. 
Hardware / software co-simulation is needed for an efficient integrated HW/SW development. Depending on the design phase this co-simulation can be done at different levels of abstraction. They range from the very abstract simulation at the specification level down to the cycle accurate simulation of hardware and the software execution on an instruction set simulator.
The goals of this project address two separate aspects. For one, we want to abstractly model the software execution environment. In addition, we want to automatically create all embedded software out of an abstract system model. 
For the modeling part, we create abstract processor models at varying level of abstraction. We seek to identify essential features for processor modeling that yield sufficiently timing accurate results in an acceptable simulation time. Due to the wide popularity of the ARM processors (and our availability of the AMBA AHB bus models), we have chosen an instruction set simulator (SWARM) for the ARM7TDMI. We integrated the ISS into the System-on-Chip Design Environment (SCE), which allows us to quickly generate cycle accurate models of custom SoC architectures. We have integrated a real-time operating system (MicroC/OS-II by Micrium) to run on top of the ISS. This gives us the ability to explore the real-time implications of the software hardware interaction. 
We have also developed a tool that automatically generates - based on the abstract model in the SLDL - the embedded software and targets the code to a chosen RTOS. This generation includes, code generation (generating software code inside each task), communication synthesis (creating drivers for internal and external communication), multi-task synthesis (targeting toward an existing RTOS, or converting to state-machine interrupt-based multi-tasking), and finally the binary creation that compiles and links everything together into a the final execution binary.

References:
  1. Hwang Y, Schirner G, Abdi S. Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support. In: Rettberg A, Zanella M, Amann M, Keckeisen M, Rammig FJ, editors. Analysis, Architectures and Modelling of Embedded Systems. Springer Berlin Heidelberg; 2009.
  2. Schirner G, Dömer R. Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling. In: In Proceedings of Design Automation and Test in Europe (DATE). Munich, Germany; 2008.
  3. Schirner G, Gerstlauer A, Dömer R. Automatic Generation of Hardware dependent Software for MPSoCs from Abstract System Specifications. In: Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC). Seoul, Korea; 2008.
  4. Schirner G, Gerstlauer A, Dömer R. Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. In: Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC). Yokohama, Japan; 2007.

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