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Novel Architecture for Streaming Applications

Hamed Tabkhi
Member:  Majid Sabbagh, Nasibeh Teimouri
Year:  2012

The exponential growth in computation demands drives chip vendors to heterogeneous architectures combining Instruction-Level Processors (ILPs) and custom HW Accelerators (HWACCs) in an attempt to provide the needed processing capabilities while meeting power/energy requirements. ILPs, on one hand, are highly flexible, but power inefficient. Custom HWACCs, on the other hand, are inflexible (focusing on dedicated kernels), but highly power efficient. Since, designing HWACCs for every application is cost prohibitive, large portions of applications still run power-hungry on ILPs. New processing architectures are needed that combine the efficiency of HWACCs while still retaining sufficient flexibility to realize applications across targeted marked segments.

One Important instance for novel architecure is Embedde vision; The goal of this project is realizing an object detection vision flow on embedded Zynq platform. Overall, Zynq 7000 SoC family considered as the state-of-the art SoCs combining both Processor System (PS) and Programmable Logic (PL) in a single chip. The PS part combines two ARM Cortex-A9 with NEON extension work up to 666 GHz clock frequency. The PL part has been fabricated at 28nm with Artix-7 FPGA.


  1. Teimouri N, Tabkhi H, Schirner G. Revisiting Accelerator-Based CMPs: Challenges and Solutions. In: Design Automation Conference (DAC). San Francisco: Design Automation Conference (DAC); In Press.
  2. Tabkhi H, Bushey R, Schirner G. Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs. In: IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). Zurich, Switzerland; 2014.
  3. Tabkhi H, Sabbagh M, Schirner G. Guiding Power/Quality Exploration for Communication-Intense Stream Processing. San Francisco, USA: 51st ACM/EDAC/IEEE Design Automation Conference (DAC); 2014.
  4. Tabkhi H, Bushey R, Schirner G. Algorithm and Architecture Co-Design of Mixture of Gaussian (MoG) Background Subtraction for Embedded Vision Processor. In: Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC).; 2013.
  5. Bushey R, Tabkhi H, Schirner G. Flexible Function-Level Acceleration of Embedded Vision Applications using the Pipelined Vision. In: Proceedings of the Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC).; 2013.

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