Fault-tolerance is now a primary design constraint for all major microprocessors; however, perfect fault-tolerance is not a requirement for most designs. Instead, designs strive to maximize performance subject to an acceptable failure rate constraint. Therefore, vendors typically set a failure rate (FIT) target for each design and validate that the design meets this target with extensive pre-silicon and post-silicon analysis. One method to quantify fault masking is to use vulnerability factors. A system consists of multiple independent components that interact through well-defined interfaces. Therefore, fault masking can be quantified within a single component by focusing on its interfaces. This abstraction is called the “vulnerability stack”, and is the major focus of this project.
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