Collaborative Research: Ultra-High Performance Carbon Nanotube Parallel Nanotube Architectures (PNAs) for On-Chip Gigascale Local & Global Interconnects
The objective of this research is to address and resolve certain critical problems of on-chip interconnects in future microprocessors that threaten to impede the progress of the microelectronics industry in less than a decade. Feasible revolutionary alternatives to overcome some of those impediments using carbon nanotube architectures are proposed. The approach is to develop highly organized ultra-high performance carbon nanotube architectures that can potentially replace and outperform existing technologies for extremely narrow (below 22 nanometers) future interconnects.
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